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TMP19A43FD

Features: (1) TX19A processor core1) Improved code efficiency and operating performance have been realized through the use of two ISA(Instruction Set Architecture) modes - 16- and 32-bit ISA modes.• The 16-bit ISA mode instructions are compatible with the MIPS16TMASE instructions of superior...

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SeekIC No. : 004524384 Detail

TMP19A43FD: Features: (1) TX19A processor core1) Improved code efficiency and operating performance have been realized through the use of two ISA(Instruction Set Architecture) modes - 16- and 32-bit ISA modes.&...

TMP19A43FD Data Sheet

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Part Number:
TMP19A43FD
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

(1) TX19A processor core
1) Improved code efficiency and operating performance have been realized through the use of two ISA
(Instruction Set Architecture) modes - 16- and 32-bit ISA modes.
• The 16-bit ISA mode instructions are compatible with the MIPS16TMASE instructions of superior code efficiency at the object level.
• The 32-bit ISA mode instructions are compatible with the TX39 instructions of superior operating performance at the object level.
2) Both high performance and low power dissipation have been achieved.
  High performance
• Almost all instructions can be executed with one clock.
• High performance is possible via a three-operand operation instruction.
• 5-stage pipeline
• Built-in high-speed memory
• DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock. Low power dissipation
• Optimized design using a low power dissipation library
• Standby function that stops the operation of the processor core
3) High-speed interrupt response suitable for real-time control
• Independency of the entry address
• Automatic generation of factor-specific vector addresses
• Automatic update of interrupt mask levels
(2) Internal program memory and data memory
• ROM correction function: 1 word × 8 blocks, 8 words × 4 blocks
(3) External memory expansion
• Expandable to 16 megabytes (for both programs and data)
• External data bus: Separate bus/multiplexed bus : Coexistence of 8- and 16-bit widths is possible. Chip select/wait controller : 4 channels
(4) DMA controller : 8 channels (2 interrupt factors)
• Activated by an interrupt or software
• Data to be transferred to internal memory, internal I/O, external memory, and external I/O
(5) 16-bit timer : 16 channels
• 16-bit interval timer mode
• 16-bit event counter mode
• 16-bit PPG output (every 4 channels, synchronous outputs are possible)
• Input capture function
• 2-phase pulse input counter function (4 channels assigned to perform this function): Multiplicationby- 4 mode
(6) 32-bit timer
• 32-bit input capture register : 4 channels
• 32-bit compare register : 8 channels
• 32-bit time base timer : 1 channel
(7) Clock timer : 1 channel
(8) General-purpose serial interface : 3 channels
• Selectable between the UART mode and the synchronization mode
(9) High-speed serial interface : 3 channels
• Selectable between the UART mode and the high-speed synchronization mode (maximum speed:
10 Mbps in the high-speed synchronization mode @40MHz)
(10) Serial bus interface : 1 channel
• Selectable between the I2C bus mode and the clock synchronization mode
(11) 10-bit A/D converter (with S/H) : 16 channels
• Start by an external trigger, and the internal timer activated by a trigger
• Fixed channel/scan mode
• Single/repeat mode
• High-priority conversion mode
• Timer monitor function
• Conversion time 1.15 µsec(@ 40MHz)
(12) 8-bit D/A converter : 2 channels
(13) Watchdog timer : 1 channel
(14) Interrupt function
• CPU: 2 factors ...................software interrupt instruction
• Internal: 46 factors.............The order of precedence can be set over 7 levels
(except the watchdog timer interrupt).
• External: 48 factors ..........The order of precedence can be set over 7 levels. Because 32 factors are associated with KWUP, the number of interrupt factors is one.
(15) Input and output ports ...............143 terminals
(16) Standby function
• Three standby modes (IDLE, SLEEP, STOP)
(17) Clock generator
• Built-in PLL (multiplication by 4)
• Clock gear function: The high-speed clock can be divided into 3/4, 1/2, 1/4 or 1/8.
• Sub-clock: SLOW and SLEEP modes (32.768 kHz)
(18) Endian: Bi-endian (big-endian/little-endian)
(19) Maximum operating frequency
• 40 MHz (PLL multiplication)
(20) Operating voltage range
• Core: 1.35 V to 1.65 V
• I/O and ADC: 2.7 V to 3.6 V
• DAC: 2.3 V to 2.7 V (21) Package P-FBGA193 (12 mm × 12 mm, 0.65 mm pitch)




Specifications

Parameter Symbol Rating Unit
  VCC15 (Core)
Vcc3 (I/O)
AVCC3(A/D)
DAVCC (D/A)
DVCC3		 − 0.3to3.0
− 0.3to3.9
− 0.3to3.9
− 0.3to3.5
− 0.3to3.9		 V
Supply voltage VIN − 0.3toVCC + 0.3 V
Low-level
output
current
High-level
output
current		 Per pin
Total
Per pin
Total		 IOL
IOL
IOH
IOH		 5
50
-5
50		 mA
Power dissipation (Ta = 85)
Soldering temperature (10 s)
Storage temperature		 PD
TSOLDER
TSTG		 600
260
−40to125		 mW

Operating
Temperature		 Exceptduring Flash W/E
During Flash W/E		 TOPR -20 to 85
0 to 70
Write/erase cycles NEW 100 cycle





Description






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