TMP1962F10AXBG

Features of the TMP1962 include the following:
(1) TX19 core processor
1) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed
• The 16-bit ISA is object-code compatible with the code-efficient MIPS16 ASE.
• The 32-bit ISA is object-code compatible with the high-performance TX39 family.
2) High performance combined with low power consumption
- High performance
• Single clock cycle execution for most instructions
• 3-operand computational instructions for high instruction throughput
• 5-stage pipeline
• On-chip high-speed memory
• DSP function: Executes 32-bit x 32-bit multiplier operations in a single clock cycle.
- Low power consumption
• Optimized design using a low-power cell library
• Programmable standby modes in which processor clocks are stopped
3) Fast interrupt response suitable for real-time control
• Distinct starting locations for each interrupt service routine
• Automatically generated vectors for each interrupt source
• Automatic updates of the interrupt mask level
(2) On-chip ROM/RAM
Product On-chip ROM On-chip RAM
TMP1962C10BXBG 1 Mbyte 40 kbyte
TMP1962F10AXBG 1 Mbyte (Flash) 40 Kbyte
Collection function on ROM (8 words x 8 blocks)
(3) External memory expansion
• 16-Mbyte off-chip address space for code and data
• External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (Separate bus/multiplex bus)
(4) 8-channel DMA controller
• Interrupt- or software-triggered
• DMA transfers between on-chip or external memory and I/O module
(5) 12-channel 8-bit timer
• 8-bit/16-bit/24-bit/32-bit interval timer mode
• 8-bit PWM mode
• 8-bit PPG mode
(6) 4-channel 16-bit timer
• 16-bit interval timer mode
• 16-bit event counter mode
• 16-bit PPG output
• Input capture function
• 2-channel dual input counter function
(7) 32-bit input capture
• 8-channel 32-bit input capture register
• 8-channel 32-bit compare register
• 1-channel 32-bit time base timer
(8) 7-channel general-purpose serial interface Either UART mode or synchronous transfer mode can be selected.
(9) 1-channel serial bus interface Either I²C bus mode or clock-synchronous mode can be selected.
(10) 24-channel 10-bit A/D converter (with internal sample/hold)
• External trigger start function
• Fixed channel/scan mode
• Single/repeat mode
• Timer monitor function
(11) Watchdog timer
(12) 4-channel chip select/wait controller
(13) Interrupt sources
• 4 CPU interrupts: software interrupt instruction
• 55 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt
• 25 external interrupts: 7 priority levels, with the exception of the NMI interrupt 1 used for an interrupt source and 14 used for KWUP
(14) 202-pin input/output ports
(15) Four standby modes
• IDLE (HALT, DOZE), STOP
(16) Clock generator
• On-chip PLL (x3)
• Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8

The TMP1962 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1962 is suitable for low-voltage and low-power applications.

The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM architecture. Additionally, the TX19 supports the MIPS16 Application-Specific Extensions (ASE) for improved code density.