TMP1962C10BXBG

The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM architecture. Additionally, the TX19 supports the MIPS16TM Application-Specific Extensions (ASE) for improved
code density.

The TMP1962 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1962 is suitable for low-voltage, low-power applications. Features of the TMP1962 include the following:
(1) TX19 core processor
1) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed
• The 16-bit ISA is object-code compatible with the code-efficient MIPS16TM ASE.
• The 32-bit ISA is object-code compatible with the high-performance TX39 family.
2) Combines high performance with low power consumption.
• High performance
• Single clock cycle execution for most instructions
• 3-operand computational instructions for high instruction throughput
• 5-stage pipeline
• On-chip high-speed memory
• DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single
clock cycle.
• Low power consumption
• Optimized design using a low-power cell library
• Programmable standby modes in which processor clocks are stopped
3) Fast interrupt response suitable for real-time control
• Distinct starting locations for each interrupt service routine
• Automatically generated vectors for each interrupt source
• Automatic updates of the interrupt mask level
(2) On-chip program memory and data memory
(3) External memory expansion
• 16-Mbyte off-chip address space for code and data
• External data bus
Separate bus/multiplexed bus: Dynamic bus sizing for 8-bit and 16-bit data ports
(4) 8-channel DMA controller
• Interrupt- or software-triggered
• Transfer destination: On-chip memory, on-chip peripherals, external memory, external peripherals
(5) 12-channel 8-bit timer
• 8/16/24/32-Bit Interval Timer mode
• 8-Bit PWM mode
• 8-Bit PPG mode
(6) 4-channel 16-bit timer
• 16-Bit Interval Timer mode
• 16-Bit Event Counter mode
• 16-bit PPG output
• Input capture
• 2-phase pulse input counter (2 channels)
(7) 32-bit input capture
• 32-bit input capture registers (8 channels)
• 32-bit compare registers (8 channels)
• 32-bit time base timer (1 channel)
(8) 7-channel general-purpose serial interface
• Either UART mode or Synchronous mode can be selected.
(9) 1-channel serial bus interface
• Either I2C Bus mode or Clock-Synchronous mode can be selected.
(10) 24-channel 10-bit A/D converter (with internal sample/hold)
• External trigger supported
• Fixed-Channel or Channel Scan mode
• Single Conversion or Continuous Conversion mode
• Timer monitoring
(11) 1-channel watchdog timer
(12) 4-channel chip select/wait controller
(13) Interrupt sources
• 4 CPU interrupts: Software interrupt instruction
• 55 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt
• 25 external interrupts: 7 priority levels, with the exception of the NMI interrupt
The external sources include 14 KWUP sources, which are all assigned to a single interrupt vector.
(14) 202-pin input/output ports
(15) Standby modes
• Two standby modes: IDLE, STOP
(16) Clock generator
• On-chip PLL (x3)
• Clock gear: Divides the high-speed clock by 1/2, 1/4 or 1/8.