TMP1941AF

(1) Four independent DMA channels
(2) Two types of bus requests, with and without bus snooping
(3) Transfer requests: Internal transfer requests: Software initiated External transfer requests: Hardware signals from on-chip peripherals and external interrupt pins
(4) Dual-address mode
(5) Memory-to-memory, memory-to-I/O, and I/O-to-memory transfers
(6) Transfer width:
• Memory: 32-bit (8-bit and 16-bit memory devices are supported through the programming of the CS/Wait Controller.)
• I/O peripherals: 8-, 16-, and 32-bit
(7) Address pointers can increment, decrement or remain constant. The user can program the bit positions at which address incrementation or decrementation occurs.
(8) Fixed channel priority

V_CC = DV_CC = AV_CC; V_SS = DV_SS= AV_SS 

Note: Maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no maximum rating value is exceeded with respect to current, voltage, power dissipation,temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning.

The TMP1941AF ADC has two mode control registers (ADMOD0 and ADMOD1), four conversion result high/low register pairs (ADREG04H/L, ADREG15H/L, ADREG26H/L, ADREG37H/L) and a clock select register (ADCCLK). The conversion result registers contain the digital values of completed conversions. The clock select register selects an A/D conversion clock.