TMC2490A

Features:

• All-digital video encoding
• Internal digital subcarrier synthesizer
• 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE 125M input format
• CCIR-624/SMPTE-170M compliant output
• Switchable chrominance bandwidth
• Switchable pedestal with gain compensation
• Pre-programmed horizontal and vertical timing
• 13.5 Mpps pixel rate
• Master or slave (CCIR656) operation
• MPEG interface
• Internal interpolation filters simplify output reconstruction filters
• 10-bit D/A converters for video reconstruction
• Supports NTSC and PAL standards
• Closed-caption waveform insertion
• Simultaneous S-Video (Y/C) output
• Controlled edge rates
• Single +5V power supply
• 44 lead PLCC package
• Parallel and serial control interface


Application

• Set-top digital cable television receivers
• Set-top digital satellite television receivers
• Studio parallel CCIR-601 to analog conversion


Pinout

Pin Descriptions
Pin Name	Pin Number	Value	Pin Function Description
Clock
PXCK	25	TTL	Pixel Clock Input. This 27.0 MHz clock is internally divided by 2 to generate the internal pixel clock. PXCK drives the entire TMC2490A, except the asynchronous microprocessor interface. All internal registers are strobed on the rising edge of PXCK.
Data Input Port
PD7-0	3844, 3	TTL	Pixel Data Inputs. Video data enters the TMC2490A on PD 7-0 (Figure 1).
Microprocessor Interface
D7-0	912,1417	TTL	Data I/O, General Purpose I/O, Chroma Input Port. When SER is HIGH, all control parameters are loaded into and read back over this 8-bit port. When SER = LOW, D 0 can serve as a composite sync output, D1 outputs a burst flag during the back porch, D2-5 are General Purpose Outputs, and D6-7 are General Purpose Inputs.
RESET	22	TTL	Master Reset Input. Bringing RESET LOW forces the internal state machines to their starting states and disables all outputs.
SA 1	4	TTL	Serial/Parallel Port Select. When SER is LOW, SA1 in conjunction with SA0 selects one of four addresses for the TMC2490A.
SA0, ADR	5	TTL	Serial/Parallel Port Select.When SER is LOW, SA0 in conjunction with SA1 selects one-of-four addresses for the TMC2490A. When SER is HIGH, this control governs whether the parallel microprocessor interface selects a table address or reads/writes table contents.

Description

The TMC2490A video encoder converts digital component video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE 125M format) into a standard analog baseband television (NTSC, NTSC-EIA, and all PAL standards) signal with a modulated color subcarrier. Both composite (single lead) and S-Video (separate chroma and luma) formats are active simultaneously at all three analog outputs. Each video output generates a standard video signal capable of driving a singlyor doubly-terminated 75 Ohm load.

The TMC2490A is intended for all non-Macrovision encoder applications.

The TMC2490A is fabricated in a submicron CMOS process and is packaged in a 44-lead PLCC. Performance is guaranteed over the full 0°C to 70°C operating temperature range.