Features: • 60 MHz computation rate
• 60 MHz data and coefficient input
• Four 11 x 10-bit multipliers
• Individual data and coefficient inputs
• 25-Bit accumulator
• Fractional and integer two's complement data formats
• Input and output data latches with user-configurable
enables
• Selectable 16-bit rounded output
• Internal 1/2 LSB rounding
• Available in 120-pin CPGA, PPGA, MPGA, or MQFPApplication• Fast pixel interpolation
• Fast image manipulation
• Image mixing and keying
• High-performance FIR filters
• Adaptive digital filters
• One- and two-dimensional image processingPinout
Specifications
| Parameter |
Min |
Max |
Unit |
| Supply Voltage |
-0.5 |
7.0 |
V |
| Input Voltage |
-0.5 |
VDD + 0.5 |
|
| Output, Applied Voltage2 |
-0.5 |
VDD + 0.5 |
V |
| Output, Externally Forced Current3,4 |
-3.0 |
6.0 |
mA |
| Output, Short Circuit Duration (single output in HIGH state to ground) |
|
1 |
sec |
| Operating, Ambient Temperature |
-20 |
110 |
°C |
| Junction Temperature |
|
140 |
°C |
| Storage Temperature |
-65 |
150 |
°C |
| Lead Soldering (10 seconds) |
|
300 |
°C |
DescriptionThe TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two's complement data. A pipelined architecture, fully registered input and output ports, and asynchronous three-state output enable control simplify the design of complex systems.
The data or coefficient inputs to the multipliers may be held over multiple clock cycles, providing storage for mixing and filtering coefficients. The 25-bit internal accumulator path allows two bits of cumulative word growth and may be internally rounded to 16 bits. Output data are updated every clock cycle, or may be held under user control. All data inputs, outputs, and controls are TTL compatible and (except for the three-state output enable) are registered on the rising edge of CLK.
The TMC2246A is uniquely suited to performing pixel interpolation in image manipulation and filtering applications. As a companion to the Fairchild Semiconductor TMC2301 and TMC2302 Image Manipulation Sequencers, the TMC2246A can execute a bilinear interpolation of an image (4-pixel ker-nels) at real-time video rates. Larger kernels or other, more complex, functions can be realized with no loss in performance by utilizing multiple devices.
With unrestricted access to all data and coefficient input ports, the TMC2246A offers considerable flexibility in applications performing digital filtering, adaptive FIR filters, mixers, and other similar systems requiring high-speed processing.
Fabricated in a submicron CMOS process, the TMC2246A operates at a guaranteed clock rate of 60 MHz over the full temperature and supply voltage ranges. It is pin- and function-compatible with Fairchild's TMC2246, while providing higher speed operation and lower power dissipation. It is available in a 120 pin Plastic Pin Grid Array (PPGA), 120 pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to PPGA (MPGA), and a 120 lead Metric Quad FlatPack (MQFP).
TMC2246A Data Sheet
