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TM5400

Features: • VLIW processor and x86 Code Morphing software provides x86-compatible mobile platform solution• 500, 533, 600, and 667 MHz operating frequencies• Integrated 64 kByte L1 instruction and data caches, and 256 kByte (TM5400) or 512 kByte (TM5600) L2 write-back cache•...

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SeekIC No. : 004523367 Detail

TM5400: Features: • VLIW processor and x86 Code Morphing software provides x86-compatible mobile platform solution• 500, 533, 600, and 667 MHz operating frequencies• Integrated 64 kByte L1...

TM5400 Data Sheet

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Part Number:
TM5400
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• VLIW processor and x86 Code Morphing software provides x86-compatible mobile platform solution
• 500, 533, 600, and 667 MHz operating frequencies
• Integrated 64 kByte L1 instruction and data caches, and 256 kByte (TM5400) or 512 kByte (TM5600) L2 write-back cache
• Integrated northbridge core logic features facilitate compact system designs
    DDR SDRAM memory controller with 100-133 MHz, 2.5V interface
    SDR SDRAM memory controller with 66-133 MHz, 3.3V interface
    PCI bus controller (PCI 2.1 compliant) with 33 MHz, 3.3V interface
• LongRun™ advanced power management with ultra-low power operation extends battery life
    0.7-2.5 W @ 500-667 MHz, 1.2-1.6V running typical multimedia applications
    100 mW in deep sleep
• Power management controls for ACPI-compliant modes
• Full System Management Mode (SMM) support
• Compact 474-pin ceramic BGA package


Specifications

Symbol Parameter Minimum Maximum
CVDD Core voltage -0.2 V 2.35 V
IOVDD 3.3V I/O voltage -0.2 V 3.6 V
IOVDD25 2.5V I/O voltage -0.2 V 3.6 V
PLLVDD PLL voltage -0.2 V 2.35 V
- IOVDD, IOVDD25 relative to CVDD, PLLVDD 0.0 V 3.465 V
Vin Input voltage -0.5 V 3.96 V
Iin Input current -100 mA 100 mA
Tstorage Storage temperature -55°C 150°C



Description

The DDR SDRAM interface is the highest performance memory interface available on the TM5400/TM5600. The DDR SDRAM controller supports only double data rate (DDR) SDRAM and transfers data at a rate that is twice the clock frequency of the interface. The DDR SDRAM controller supports the equivalent of two DIMMs (up to four rows) of double data rate (DDR) SDRAM using a 64-bit wide interface.

The DDR SDRAM can be populated with 64-Mbit, 128-Mbit, or 256-Mbit devices. For the highest performance, it is recommended that the DDR SDRAM devices be soldered to the planar rather than incorporated on DIMMs. Also, to reduce signal loading, only x8, x16 or x32 devices should be used. Table 1 shows possible DDR SDRAM configurations for a TM5400/TM5600-based system.




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