Features: 2` 1 to 2.6 Gigabits Per Second (Gbps)
Serializer/Deserializer
` Independent Transmit/Receive Channels for
Asynchronous Data Rate Operation
` Fast Relock at 1.25 Gbps and 2.5 Gbps for
EPON OLT Applications
` Hot-Plug Protection
` High-Performance 80-Pin TQFP Package (PFP)
` 2.5-V Power Supply for Low Power Operation
` Programmable Preemphasis Levels on Serial
Output
` Interfaces to Backplane, Copper Cables, or
Optical Converters
` On-Chip 8-bit/10-bit Encoding/Decoding
` On-Chip PLL Provides Clock Synthesis From
Low-Speed Reference
` Receiver Differential Input Thresholds 200 mV
Minimum
` 3 V Tolerance on Parallel Data Input Signals
` Selectable 10 or 20 bit Parallel TTL Compatible
Data Interface
` Industrial Temperature Range 40 to 85
` Integrated 50- Termination Resistors on RX
` Transmit FIFO Decouples Transmit Clock
From Reference ClockApplication· Next Generation EPON OLT Systems
· Ideal for use with EPON OLT MAC Solutions
such as TK3723 from Teknovus
· Gigabit Ethernet and Fibre Channel LinksPinout
Specifications
| |
VALUE |
UNIT |
| VDD Supply voltage(2) |
0.3 to 3 |
V |
Voltage range at TXD[0:19], ENABLE, TX_CLK, LOOPEN, PRBSEN, PRE, CTRL0,
CTRL1, TXRATE, RXRATE, REFCLK, LCKREFN, TESTEN,RXCODE |
0.3 to 4 |
V |
| Voltage range at any other terminal except above |
0.3 to VDD+ 0.3 |
V |
| PD Package power dissipation |
See Dissipation Rating Table |
|
| Tstg Storage temperature |
65 to 150 |
|
| Electrostatic discharge |
HBM |
2 |
kV |
| CDM |
1.5 |
kV |
| TA Characterized free-air operating A temperature range |
PFP |
40 to 85 |
|
1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are stated with respect to network ground.
DescriptionThe TLK2541 is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use in high-speed bidirectional point-to-point data transmission systems. The TLK2541 supports an effective serial interface speed of 1 Gbps to 1.3 Gbps or 2 to 2.6 Gbps, providing over 2 Gbps of data bandwidth.
The primary application of this TLK2541 is to provide high-speed I/O data channels for point-to-point baseband data
transmission over controlled impedance media of approximately 50. The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The TLK2541 allows for independent transmit and receive data rate operation for applications that need asymmetrical data rates such as Passive Optical Networking.
This TLK2541 can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over parallel solutions, as well as scalability for higher data rates.
At full rate, the TLK2541 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.6 Gbps. The transmitter latches 20 parallel data at a rate based on the supplied transmit clock (TX_CLK).. The 20-bit word is then transmitted differentially at 20 times the reference clock (REFCLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (RX_CLK). It then outputs the 20 bit recovered word on the receive data terminals RXD[0:19]. If the internal 8B/10B coding and decoding logic is enabled, 16 bits of data and two bits of control are latched on TX_CLK and the data is encoded into a 20 bit data word to be serialized. Likewise the 20 bit received data word is decoded into a 16 bit data word plus two bits of decode status.
TLK2541 Data Sheet
