Features: 10-Bit Resolution 20 MSPS SamplingAnalog-to-Digital Converter (ADC)Power Dissipation . . . 107 mW Typ5-V Single Supply OperationDifferential Nonlinearity . . . ±0.5 LSB TypNo Missing CodesPower Down (Standby) ModeThree State OutputsDigital I/Os Compatible With 5-V or 3.3-VLogicAdjustable...
TLC876C: Features: 10-Bit Resolution 20 MSPS SamplingAnalog-to-Digital Converter (ADC)Power Dissipation . . . 107 mW Typ5-V Single Supply OperationDifferential Nonlinearity . . . ±0.5 LSB TypNo Missing Codes...
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Communications
Multimedia
Digital Video Systems
High-Speed DSP Front-End ...TMS320C6x
The TLC876C is a CMOS, low-power, 10-bit, 20 MSPS analog-to-digital converter (ADC). The speed, resolution, and single-supply operation are suited for applications in video, multimedia, imaging, high-speed acquisition, and communications. The low-power and single-supply operation satisfy requirements for high-speed portable applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Force and sense connections to the reference inputs provide a more accurate internal reference voltage to the reference resistor string.
A standby mode of operation reduces the power to typically 15 mW. The TLC876C to either 5-V or 3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876C distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the fifth stages operate on the four preceding samples.