TL4810BI

Pinout

Specifications

Logic supply voltage, V_CC1 (see Note 1)  . . . . . . . . . . . ........ . . . . . .18 V
Driver supply voltage, V_CC20  . . . .. . . .. . . . . . . . . . . . . ........ . . . . . .70 V
Output voltage, VO  . . . . . . . .  . . . . . . . . . . . . . . . . ........ . . . . . . . . .70 V
Input voltage range, V_I  . . . .. . . . . . . . . . . ........ .0.3 V to V_CC1 + 0.3 V
Continuous total power dissipation . . .See Dissipation Rating Table
Operating free-air temperature range, T_A: TL4810B  . . ........ 0  to 70
TL4810B_I  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ . . . . -40  to 85
Storage temperature range, Tstg  . . . . . . . . . . . ........ . .65  to 150 
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds    .260

NOTE 1: Voltage values are with respect to GND.


Description

The TL4810B and TL4810BI are monolithic BIDFET† integrated circuits designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large
display arrays.

A 10-bit data word is serially loaded into the shift register on the positive-going transitions of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while LATCH ENABLE is high and is latched when LATCH ENABLE is low. When BLANKING is high, all outputs are low.

Outputs are totem-pole structures formed by npn emitter-follower and double-diffused MOS (DMOS) transistors with output voltage ratings of 70 V and 40-mA source-current capability. All inputs are compatible with CMOS and TTL levels, but each requires the addition of a pullup resistor to VCC1 when driven by TTL logic.

The TL4810B is characterized for operation fromn 0  to 70 . The TL4810BI is characterized for operation from 40  to 85 .