TISP61511D

On-State RMS Current (It RMS) :
Forward Voltage Drop :
Gate Trigger Voltage (Vgt) :
Maximum Gate Peak Inverse Voltage :
Gate Trigger Current (Igt) :
Holding Current (Ih Max) :
Breakover Current IBO Max :
Packaging : Tube
Off-State Leakage Current @ VDRM IDRM : 0.005 mA
Mounting Style : SMD/SMT
Rated Repetitive Off-State Voltage VDRM : 100 V
Package / Case : SOIC-8


Pinout




Specifications

RATING	SYMBOL	VALUE	UNIT
Repetitive peak off-state voltage, IG = 0, -40°C TJ85°C	VDRM	-100	V
Repetitive peak gate-cathode voltage, VKA = 0, -40°C TJ 85°C	VGKRM	-85	V
Non-repetitive peak on-state pulse current (see Notes 1 and 2)         10/1000 µs         5/310 µs         0.2/310 µs         1/20 µs         2/10 µs                                                                                                                        TJ = -40°C                                                                                                                     TJ = 25, 85°C	ITSP	30 40 40 90 120 170	A
Non-repetitive peak on-state current, 50 Hz (see Notes 1 and 2)            full-sine-wave, 20 ms            1 s	ITSM	5 3.5	A
Non-repetitive peak gate current, half-sine-wave, 10 ms (see Notes 1and 2)	IGSM	2	A
Junction temperature	TJ	-55 to +150	°C
Storage temperature range	Tstg	-55 to +150	°C

Description

The TISP61511D and TISP61512P are dual forward-conducting buffered p-gate overvoltage protectors. They are designed to protect monolithic Subscriber Line Interface Circuits,SLICs, against overvoltages on the telephone line caused by lightning, ac power contact and induction. The TISP61511D and TISP61512P limit voltages that exceed the SLIC supply rail voltage.

The TISP61511D and TISP61512P SLIC line driver section is typically poweredfrom 0 V (ground) and a negative voltage in the region of -10 V to -70 V. The protector gate is connected tothis negative supply. This references the protection (clipping) voltage to the negative supply voltage. As theprotection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimised.

TISP61511D and TISP61512P Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition. As the current subsides the high holdingcurrent of the crowbar prevents d.c.latchup.

These monolithic protection devices TISP61511D and TISP61512P are fabricated in ion-implanted planar vertical power structures for high reliability and in normal system operation they are virtually transparent. The buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction.