Features: • Second-Generation PLD Architecture• High-Performance Operation: fmax (External Feedback) . . . 71 MHz Propagation Delay . . . 10 ns Max• Increased Logic Power Up to 22 Inputs and 10 Outputs• Increased Product Terms Average of 12 Per Output• Variable Prod...
TIBPAL22V10C: Features: • Second-Generation PLD Architecture• High-Performance Operation: fmax (External Feedback) . . . 71 MHz Propagation Delay . . . 10 ns Max• Increased Logic Power Up to 22...
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Features: SpecificationsDescription TIBPAL 16L8-15C is a kind of programmable array logic device.I...
Features: SpecificationsDescription TIBPAL 16L8-20M is a kind of programmable array logic device.T...
PinoutSpecificationsSupply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . ....
The TIBPAL22V10-10C is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) logic structure featuring the new concept "Programmable Output Logic Macrocell". These IMPACT-XE circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22V10-10C offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible.
A power-up clear function of TIBPAL22V10A is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs TIBPAL22V10A selected as active-low power up with their outputs high. Registered outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will appear to be open. The TIBPAL22V10-10C is characterized for operation from 0°C to 75°C.