THS1240

Supply voltage range: AV_DD  . . . . . . . . . . . . . . . . 0.5 V to 7 V
DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V 
DRV_DD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage between AV_SS and DVSS and DRV_SS  . . . .0.3 V to 0.5 V
Voltage between DRV_DD and DV_DD. . . . . . . . . . . . .0.5 V to 5 V
Voltage between AV_DD and DV_DD  . . . . . . . . . . . . . 0.5 V to 5 V
Digital data output  . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to DVDD+0.3 V
CLK peak input current, Ip_(CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Peak total input current (all inputs), Ip . . . . . . . . . . . . . . . . . . . . .  30 mA
Operating free-air temperature range, TA:THS1240C . . . . . . . . 0°C to 70°C 
THS1240I  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C
Storage temperature range  . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds  . . . . .260°C 

The THS1240 is a high-speed low noise 12-bit CMOS pipelined analog-to-digital converter. A differential sample and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog input. A buffered analog input of THS1240 enables operation with a constant analog input impedance, and prevents transient voltage spikes from feeding backward to the analog input source. Full temperature DNL performance allows for industrial application with the assurance of no missing codes. The THS1240 can operate with either internal or external references. Internal reference usage selection is accomplished simply by externally connecting reference output terminals to reference input terminals.

The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible bandwidth. The differential analog inputs of THS1240 are terminated with a 1-kΩ resistor. The inputs are then fed to a unity gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs the final 12 bits.