THS1050

50 MSPS Maximum Sample Rate
10-Bit Resolution
No Missing Codes
On-Chip Sample and Hold
73 dB Spurious Free Dynamic Range at f_in = 15.5 MHz
5 V Analog and Digital Supply
3 V and 5 V CMOS Compatible Digital Output
9.7 Bit ENOB at fIN = 31 MHz
60 dB SNR at fIN = 31 MHz
82 MHz Bandwidth
Internal or External Reference
Buffered 900 W Differential Analog Input

The THS1050 is a high speed low noise 10-bit CMOS pipelined analog-to-digital converter. A differential sample and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog input. A buffered analog input enables operation with a constant analog input impedance, and prevents transient voltage spikes from feeding backward to the analog input source. Full temperature DNL performance allows for industrial application with the assurance of no missing codes. The typical integral nonlinearity (INL) for the THS1050 is lessthan one LSB. The superior INL curve of the THS1050 results in SFDR performance that is exceptional for a 10-bit analog-to-digital converter. The THS1050 can operate with either internal or external references. Internal reference usage selection is accomplished simply by externally connecting reference output terminals to reference input terminals.

The THS1050 uses a differential pipeline architecture and assures no missing codes over the full operating temperature range. The THS1050 uses a 1 bit per stage architecture in order to achieve the highest possible bandwidth. The differential analog inputs are terminated with a 900-W resistor. The inputs of THS1050 are then fed to a unity gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational amplifier based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram. The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic block which then outputs the final 10 bits.