Features: ` Dual-convergence voiceband echo canceller (EC).` 32 independent and individually controlled echo canceller channels.` Stable performance across virtually all network hybrid conditions.` Multiple-channel processing modes: - Echo cancelling ON/OFF. - -law to A-law and A-law to -law conve...
TECO3264: Features: ` Dual-convergence voiceband echo canceller (EC).` 32 independent and individually controlled echo canceller channels.` Stable performance across virtually all network hybrid conditions.` ...
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Parameter |
Symbol |
Min |
Max |
Unit |
Input Voltage* |
VI |
VSS+0.3 |
VDD+0.3 |
V |
dc Supply Voltage |
VDD VSS |
- |
3.3 |
V |
VDD5 VSS |
- |
5.5 |
V | |
Power Dissipation |
PD |
- |
1.43 |
W |
Storage Temperature |
Tstg |
-40 |
125 |
|
Junction Temperature |
TJ |
- |
125 |
* In 5 V tolerant input mode, maximum input voltage is VDD5 + 0.5 V.
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
The TECO3264 32-channel echo canceller (EC) device is a 3.3 V, CMOS, very large-scale integration (VLSI) component offering 32 independent channels of echo cancellation. Packaged in a 160-pin, plastic, metric quad flat pack with heat speader (MQFPH) and handling up to 64 ms of tail-end delay, this device combines high performance, high channel density, low power dissipation, high flexibility, excellent maintenance capability, and low cost into a single package.
The TECO3264 32-channel echo canceller provides echo cancellation for both T1 and E1 systems. The device operates from a single 3.3 V supply and requires only an external 8.192 MHz clock and 8 kHz frame sync.
Built-in self-test logic affords easy device verification while integrated boundary-scan capability reduces board verification time and cost.
A high-speed microprocessor interface and full user provisionability on device pins provide maximum flexibility.