TDA9141

GENERAL DESCRIPTION
   The TDA9141 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor. The TDA9141 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL comb filter. The IC can process CVBS signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected a line-locked clock (LLC) signal is available at the output port pin. A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal (search tuning mode). Two pins with an input/output port and an output port of the I2C-bus are available. The I2C-bus address of the TDA9141 is hardware programmable.