TDA10085HT

Note
1. Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability.

The TDA10085HT is a single-chip channel receiver for satellite television reception matching both DSS and DVB-S standards. The device contains a dual 6-bit flash ADC, variable rate BPSK/QPSK coherent demodulator and forward error correction functions. The ADC interfaces directly with I and Q analog baseband signals. After analog-to-digital conversion, the TDA10085 implements a bank of cascadable filters as well as anti-alias and half-Nyquist filters. An analog AGC signal is generated using an amplitude estimation function. The TDA10085 performs clock recovery at twice the baud rate and achieves coherent demodulation without any feedback to the local oscillator. Forward error correction is built around two error-correcting codes: a Reed-Solomon (outer code) and a Viterbi decoder (inner code). The Reed-Solomon decoder corrects up to 8 erroneous bytes among the N (204) bytes of one data packet. A convolutional de-interleaver is located between the Viterbi output and the Reed-Solomon decoder input. The de-interleaver and Reed-Solomon decoder TDA10085HT are automatically synchronized according to a frame synchronization algorithm that uses the sync pattern present in each packet. The TDA10085 is controlled via an I2C-bus interface. The circuit operates at sampling frequencies up to 100 MHz, can process variable modulation rates and achieves transmission rates up to 45 Mbaud. Furthermore, for dish control applications, hardware supports DiSEqc 1.x with control access via the I2C-bus.

An interrupt line that can be programmed to activate on events or on timing information is provided.

Designed in 20 micron CMOS technology and housed in a TDA10085HT package, the TDA10085 operates over the commercial temperature range.