TCMD0110G

Features: `Operation to 12.5 Gbits/s NRZ.` Internal optional retiming flip-flop to minimize output data pattern jitter.` Adjustable output amplitude up to 3 V (RL = 50 ).` Integrated dc level adjustment to 1.5 V` Complementary data and clock inputs, and data output.` Complete operation and control...

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SeekIC No. : 004515683 Detail

TCMD0110G: Features: `Operation to 12.5 Gbits/s NRZ.` Internal optional retiming flip-flop to minimize output data pattern jitter.` Adjustable output amplitude up to 3 V (RL = 50 ).` Integrated dc level adjust...

floor Price/Ceiling Price

Part Number:
TCMD0110G
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/4

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Product Details

Description



Features:

` Operation to 12.5 Gbits/s NRZ.
` Internal optional retiming flip-flop to minimize output data pattern jitter.
` Adjustable output amplitude up to 3 V (RL = 50 ).
` Integrated dc level adjustment to 1.5 V
` Complementary data and clock inputs, and data output.
` Complete operation and control with single 5.2 V power supply.
` 28 ps rise and fall time (20%-80%).
` 2 ps typical rms jitter (clocked mode).
` Clock disable mode for data feed-through.
` Optional 50 on-chip termination for unused output (die form only).
` Single or dual-pin pulse width adjust 80 ps-120 ps.
` Available in die form or a 32-pin microlead frame package.



Application

· Optical transmitters.
· Digital video transmission.
· SONET/SDH test equipment.
· SONET/SDH OC-192/STM-64 transmission systems.
· 10.7 Gbits/s and 12.5 Gbits/s forward error correction (FEC).
· 10G Ethernet 10.3125 Gbits/s.



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Min
Max
Unit
Storage Temperature
Tstg
-40
125
°C
Supply Voltage
Vss
-5.5
0
V
Supply Current
Iss
-
400
mA
Input Voltage
VDATAP, VDATAN
-2.0
0.5
V
Output Voltage
VDOUTP, VDOUTN
-4.1
0.5
V
Modulation Control Voltage
VMOD
Vss 0.5
Vss + 1.5
V
Offset Control Voltage
VBIAS
Vss 0.5
Vss + 2.5
V
Pulse Width Control Voltage
VPWP, VPWN
Vss 0.5
Vss + 2.5
V
Modulation Current
IVMOD
-3
3
mA



Description

The TCMD0110G has been designed to drive electroabsorption modulators (EAMs), electroabsorption modulated lasers (EMLs), Mach-Zehnder (M-Z) lithium niobate modulators, and direct modulated lasers (DMLs) that have a 50 input impedance at speeds up to 12.5 Gbit/s NRZ. For nonclocked applications,a clock disable pin is provided.

The driver consists of an input buffer TCMD0110G, a limiting amplifier, a selectable data retiming section, a pulse width control circuitry, an output buffer with adjustable modulation level, and a dc offset section to provide a mark level adjustment.

The output buffer is designed to provide 3 V of modulation to a 50 load at each output. The dc offset adjustment networks provide down to 1.5 V offset (see Figure 7). The dc offset for the unused output can be disabled to minimize power consumption (see Table 1).

The input data TCMD0110G is retimed using an integrated flip-flop to remove incoming pattern dependent jitter. This feature is enabled using a clock select pad (see Table 1). If no clock is available, the TCMD0110G can be operated in a nonclocked mode.

The unused output can be terminated through the integrated 50 resistor when using the die form of the product(see Table 1).




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