TC9418FN

DescriptionThe TC9418FN is a PLL LSI for digital tuning system (DTS) incorporating a 2-modulus prescaler.Each function is controlled through four serial bus lines,allowing you to configure a high performance digital tuning system. Features of the TC9418FN are:(1)comes with a 17bit programmable co...

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SeekIC No. : 004515300 Detail

TC9418FN: DescriptionThe TC9418FN is a PLL LSI for digital tuning system (DTS) incorporating a 2-modulus prescaler.Each function is controlled through four serial bus lines,allowing you to configure a high pe...

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Part Number:
TC9418FN
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/12

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Description



Description

The TC9418FN is a PLL LSI for digital tuning system (DTS) incorporating a 2-modulus prescaler.Each function is controlled through four serial bus lines,allowing you to configure a high performance digital tuning system.

Features of the TC9418FN are:(1)comes with a 17bit programmable counter, two parallel output phase comparators, a 75kHz crystal oscillator, a reference counter, and a 20bit IF counter; (2)consisting of a 75kHz crystal resonator (X'tal), the oscillator circuit is powered by a constant-voltage power supply to generate consistently stable oscillation; (3)the reference frequency can be selected from seven frequencies available(fref=1kHz, 3k, 3.125k, 5k, 6.25k, 12.25k, 25k); (4)ideal for configuring a digital tuning system in headphone stereos and portable radios.

The absolute maximum ratings of the TC9418FN can be summarized as:(1)supply voltage:-0.3 to 6.0V;(2)input voltage:-0.3 to Vdd+0.3V;(3)storage temperature:-55 to 150;(4)power dissipation:400mW;(5)operating temperature:-10 to 60.As shown in the block diagram, the TC9418FN has 32bit and 12bit registers providing a total of 44bits to set data for control of each function. Each data in these registers is transferred to and from the controller through serial ports using the DIN, ROUT, CK, and CE pins. The data serially transferred in one operation consists of eight address bits and 32 data bits, 40bits in total. However,the serially transferred data to set the I/O and DO pins (input mode 2) consists of eight address bits and 16 data bits, 24bits in total.Some of the eight address bits above can be omitted, to a minimum of four bits. In this case, use these four bits to specify the address(Clock can also be omitted.).Measurement with a general-purpose IF counter is accomplished by setting a gate time according to the IF input's frequency band and then setting the START bit to 1 to start the IF counter.In this case, since the PLL's divide number data and the START bit are in the same data, a wait time is provided.To set this wait time, the same W1 and W0 bits are used that are used to set a wait time for unlock detection.




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