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TC9205M

Features: Stand Alone Switch On A Chip 5 Ethernet 10/100/1000 portsI Ethernet 10/100 portMII/GMII interface for 5 portsI extra MII interface for 6th portFour Classes of Service (CoS) selectable foreach port and/or checked via IP Header and802.1Q VLAN TagFive port-based VLANsMaximum throughput, non...

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SeekIC No. : 004515228 Detail

TC9205M: Features: Stand Alone Switch On A Chip 5 Ethernet 10/100/1000 portsI Ethernet 10/100 portMII/GMII interface for 5 portsI extra MII interface for 6th portFour Classes of Service (CoS) selectable fore...

TC9205M Data Sheet

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Part Number:
TC9205M
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

Stand Alone Switch On A Chip          
5 Ethernet 10/100/1000 ports
I Ethernet 10/100 port
MII/GMII interface for 5 ports
I extra MII interface for 6th port
Four Classes of Service (CoS) selectable for
each port and/or checked via IP Header and
802.1Q VLAN Tag
Five port-based VLANs
Maximum throughput, non head-of-line
blocking architecture
Embedded SSRAM packet buffer/address table
8K MAC address table
Each port is configurable to 10 full/half duplex,
100 full/half duplex and 1000 full duplex mode
Flow-control ability is able to set for both full
and half duplex mode
Broadcast throttling
Port Mirroring
Serial EEPROM Interface, EEPROM is optional
MDIO master for PHY configuration / polling
0.18 micron technology
2V and 3.3V dual voltage power supply
Packaged in PBGA 292
25MHz crystal input only


Pinout

Connection Diagram


Description

TC9205M is a fully integrated 5 Port 10/100/1000 smart Ethernet switch controller designed for low cost and high performance solutions. The chip embeds necessary SSRAM for packet buffering and MAC address table. TC9205M provides MII / GMII / interface for all ports.

A store-and-forward switching method using a non-blocking architecture is implemented within TC9205M to improve the availability and bandwidth. The chip embeds packet buffer, which it supports normal and priority queues for each transmission port.

TC9205M provides evolved CoS with four levels of priority. The priority can be checked via layer 2 (802.1Q VLAN Tagging) and/or layer 3 (IP Header TOS bits) packets. Port based priority is also provided to ensure transmission with precedence for all packets incoming from selected port(s).




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