TC90A36F

The TC90A36F converts YUV signals with 50Hz or 60Hz of fv (Vvertical frequency) into YUV signals with 100Hz or 120Hz of fv with a field doubling method. TC90A36F includes two channels of AID converter, three channels of D/A converter, an interface for an external FIFO memory, a clamp circuit for Y signal input and so on. A field doubling system can be completed with TC90A36F, VCOs and a 4 Meg FIFO memory.

Features of the TC90A36F are:(1)horizontal time compression and expansion for a wide screen TV; (2)picture freeze mode; (3)two channels of 8-bit A/D converter; (4)three channels of 8-bit D/A converter; (5)I2C bus interface; (6)power supply voltage:5V.For double-scan conversion, the clock used to read data needs double the frequency of the clock used to write data in memory.TC90A36F controls for write input HD signal and phase compare AFC. For read, to avoid skew in the upper screen, TC90A36F controls the frequency compare AFC. Thus, a separate PLL VCO is required for read and write.

The absolute maximum ratings of the TC90A36F can be summarized as:(1)power supply voltage:-0.3 to 7 V;(2)input voltage:-0.3 to Vdd+0.3V;(3)storage temperature:-40 to 125;(4)power dissipation:1530mW.The IC features a function for adding a side panel. The side panel level can be varied using the Y signal only (YSPL at sub-address:22 HEX). Set the timing by setting to the first part of H blanking using register HSPS (sub-address:15 HEX); reset the timing by setting to the latter part of H blanking using register HSPR (sub-address:16 HEX). If a side panel is not added to the output picture, set the output level to the same as the Y blanking level and set the timing to other than the picture period.Data are transferred on the SDA line in units of 8bits in sync with the clock for the SCL line.Transfer start and end are controlled by changing SDA when the SCL line is at high level.Acknowledge in units of bytes is defined so that when 8-bit data are transferred, 1-bit acknowledge is transferred.