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TC74AC112P

Features: • High speed: fmax = 170 MHz (typ.) at VCC = 5 V• Low power dissipation: ICC = 4 A (max) at Ta = 25• High noise immunity: VNIH = VNIL = 28% VCC (min)• Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 transmission lines.• Bala...

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TC74AC112P: Features: • High speed: fmax = 170 MHz (typ.) at VCC = 5 V• Low power dissipation: ICC = 4 A (max) at Ta = 25• High noise immunity: VNIH = VNIL = 28% VCC (min)• Symmetrical o...

TC74AC112P Data Sheet

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Part Number:
TC74AC112P
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
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  • 15 Days
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Product Details

Description



Features:

• High speed: fmax = 170 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 A (max) at Ta = 25
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
   Capability of driving 50 transmission lines.
• Balanced propagation delays: tpLH tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F112


Pinout

Connection Diagram


Specifications

Parameter Symbol Value Unit
DC Supply Voltage VCC -0.5 to +7.0 V
DC Input Voltage VIN -0.5 to VCC +0.5 V
DC Output Voltage VOUT -0.5 to VCC +0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current IOUT ±50 mA
DC VCC/ground current ICC ±100 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature Tstg -65 to +150

Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.

Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges.

Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).

Note 2: 500 mW in the range of Ta = −40 to 65. From Ta = 65 to 85 a derating factor of −10 mW/ should be
applied up to 300 mW.


Description

The TC74AC112P is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

In accordance with the logic level given J and K input this device changes state on negative going transition of the clock pulse. CLEAR and PRESET of the TC74AC112P are independent of the clock and accomplished by a low logic level on the corresponding input.

All inputs of the TC74AC112P are equipped with protection circuits against static discharge or transient excess voltage.




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