PinoutSpecifications Characteristics Symbol Rating Unit DC supply voltage VDD1 VSS1 − 0.5~VSS1 + 20 V VDD2 VSS1 − 0.5~VDD1 + 0.5 V Input voltage VIN VSS1 − 0.5~VDD1 + 0.5 V Output voltage VOUT VSS1 − 0.5~VDD1 + 0.5 V DC input current IIN ...
TC4521BP: PinoutSpecifications Characteristics Symbol Rating Unit DC supply voltage VDD1 VSS1 − 0.5~VSS1 + 20 V VDD2 VSS1 − 0.5~VDD1 + 0.5 V Input voltage VIN VSS1 − ...
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Characteristics | Symbol | Rating | Unit |
DC supply voltage | VDD1 | VSS1 − 0.5~VSS1 + 20 | V |
VDD2 | VSS1 − 0.5~VDD1 + 0.5 | V | |
Input voltage | VIN | VSS1 − 0.5~VDD1 + 0.5 | V |
Output voltage | VOUT | VSS1 − 0.5~VDD1 + 0.5 | V |
DC input current | IIN | ±10 | mA |
Power dissipation | PD | 300 | mW |
Operating temperature range | Topr | −40~85 | |
Storage temperature range | Tstg | −65~150 |
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
TC4521BP is frequency divider consisting of 24 stages of flip-flop. The input section is equipped with an inverter to enable to use either RC oscillator circuit or crystal oscillator circuit and to accept pulse from external clock source.
Each flip-flop of TC4521BP TC4521BP is inverted by the falling edge of the output of previous stage flip-flop and this can count up to the maximum of 224 = 16,777,216.
Since six outputs, 218, 219, 220, 221, 222, and 223 are available besides of 224, adjustment of frequency divided output can be achieved.