Features: · Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B
· Pin Equivalent to General Trade 26LS32
· High Input Impedance Approximately 8 kW
· 4-ns Maximum Propagation Delay
· TB5R1 Provides 50-mV Hysteresis
· TB5R2 With -125-mV Threshold Offset for Preferred State Output
· -1.1-V to 7.1-V Common Mode Range
· Single 5-V ±10% Supply
· Slew Rate Limited (1 ns min 80% to 20%)
· TB5R2 Output Defaults to Logic 1 When In- puts Left Open or Shorted to VCC or GND
· ESD Protection HBM > 3 kV, CDM > 2 kV
· Operating Temperature Range: -40°C to 85°C
· Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
Application· Digital Data or Clock Transmission Over Bal- anced Lines
Pinout
Specificationsover operating free-air temperature range unless otherwise noted(1)
|
UNIT |
| Supply voltage, VCC |
0 V to 6 V |
| Magnitude of differential bus (input) voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| |
8.4 V |
| ESD |
Human Body Model(2) |
All pins |
±3 kV |
| Charged-Device Model(3) |
All pins |
±2 kV |
| Continuous power dissipation |
See Dissipation Rating Table |
| Storage temperature, Tstg |
-65 to 150 |
(1) Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
DescriptionThese quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.
The TB5R1 is a pin- and function-compatible replace-ment for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection.
The TB5R2 is a pin- and function-compatible repla-cement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protec·tion. The TB5R2 preferred state feature places the high state when the inputs are open, shorted to ground, or shorted to the power supply.
The power-down loading characteristics of the re- ceiver input circuit are approximately 8 kW relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.
The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D).
The enable inputs of this device include internal pullup resistors of approximately 40 kW that are connected to VCC to ensure a logical high level input if the inputs are open circuited.
TB5R1 Data Sheet
