TAS1020A

` Universal Serial Bus (USB)
` USB specification version 1.1 compatible
` USB audio class specification 1.0 compatible
` Integrated USB transceiver
` Supports 12 Mb/s data rate (full speed)
` Supports suspend/resume and remote wake-up
` Supports control, interrupt, bulk, and isochronous data transfer types
` Supports up to a total of seven IN endpoints and seven OUT endpoints in addition to the control endpoint
` Data transfer type, data buffer size, single or double buffering is programmable for each endpoint
` On-chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive synchronization modes for isochronous endpoints
` To support synchronization for streaming USB audio data, the ACG can be used to generate the master clock for the codec
` Micro-Controller Unit (MCU)
` Standard 8052 8-bit core
` 8K bytes of program memory ROM that contains a boot loader program and a library of commonly used
USB functions
` 6016 bytes of program memory RAM which is loaded by the boot loader program
` 256 bytes of internal data memory RAM
` Two GPIO ports
` MCU handles all USB control, interrupt, and bulk endpoint transfers
` DMA Controller
` Two DMA channels to support streaming USB audio data to/from the codec port interface
` Each channel can support a single USB isochronous endpoint
` In the I2S mode the device can support DAC/ADCs at different sampling frequencies
` A circular programmable FIFO used for isochronous audio data streaming
` Codec Port Interface
` Configurable to support AC'97 1.X, AC'97 2.X, AIC or I2S serial interface formats
` I2S modes can support a combination of one DAC and/or two ADCs
` Can be configured as a general-purpose serial interface
` Can support bulk data transfer using DMA for higher throughput
` I2C Interface
` Master only interface
` Does not support a multimaster bus environment
` Programmable to 100 kb/s or 400 kb/s data transfer speeds
` Supports wait states to accommodate slow slaves
` General Characteristics
` High performance 48-pin TQFP Package
` On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz crystal input
` Reset output available which is asserted for both system and USB reset
` External MCU mode supports application firmware development
` 8K ROM with boot loader program and commonly used USB functions library
` 3.3 V core and I/O buffers

Supply voltage range, DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 to 3.6 V
Input voltage range, V_I: 3.3 V TTL/LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DD + 0.5 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0 to 70
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  300

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.