TAAD08JU2

` System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC) applications.
` IC provides an integrated octal framer that supports T1/E1/J1 formats.
` Supports inverse multiplexing for ATM (IMA) over selected group and link mappings ranging from four two-link groups up to one eight-link group per ATM Forum AF-PHY-0086.001.
` Integrates an ATM adaptation layer 2 (AAL2) segmentation and reassembly (SAR) function for support of low-speed data or voice traffic per ITU I.363.2.
` Provides AAL5 SAR functionality per ITU I.363.5.
` Provides quality of service (QoS) connection identifier (CID) multiplexing per ITU I.366.1.
` Enables ATM layer user network interface (UNI) or IMA mode, selectable on a per-link basis for flexible transport of delay critical voice and data traffic.
` Guarantees QoS for a variety of traffic types (including delay-sensitive voice, real-time data, non-real-time data, and signaling information) through an advanced hierarchical three-level priority scheduler and per-VC queueing.
` Supports 2032 bidirectional AAL2 CIDs.
` Supports 2032 bidirectional high-speed data connections or virtual circuits (VCs) via embedded context memory; filters control cells and accepts control cells via a host microprocessor interface.
` On-board memory is used for connection management and queue data storage. No external memory is needed.
` Software package includes the following:
- Device manager source code (C-based device manager ready-to-use with host RTOS).
- Setup file utility to provision TAAD08JU2.
- Firmware for embedded controller (executable binary).
- API reference manual available for device manager software.
` Designed in 0.16 m, low-power CMOS technology.

* This maximum rating only applies when the device is powered up with V_DD.

TAAD08JU2 provides a flexible network-interface solution for next-generation applications in which efficient transport of narrowband voice and broadband data information is critical to guaranteeing network QoS for the user and transmission efficiency for the network operator. Constructed using Agere's 0.16 m CMOS technology, the chip has an integrated octal framer, IMA processor, cell scheduler and router, and AAL2/5 SAR functions.

TAAD08JU2 operates in either UNI or IMA mode (selectable on a per-span line basis). The complete AF-PHY- 0086.001 management information base (MIB) is supported. Flexible provisioning of link and group combinations enables a mix of IMA and UNI mappings to various AAL services.

Support for AAL2 is provided via an AAL/CPS function that maps/demaps variable-sized CPS packets to/from ATM-SDU. A total of 2032 bidirectional CIDs are supported. These CIDs can be transported within a programmable number of VCs per direction. TAAD08JU2 supports up to 124 AAL2 VCs, which may be allocated between ingress and egress traffic.

Support for high-speed data switching is provided whereby AAL5 VCs are routed through to the system interface toward their destinations. TAAD08JU2 provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory.
TAAD08JU2 provides the following:
`Integrated policing
`F4/F5 operations, administration, and maintenance (OAM)
` Cell processing
`Statistics collection for performance monitoring
Communication with TAAD08JU2 is accomplished through a 32-bit microprocessor interface. The system interface is through two choices: a UTOPIA 2 interface with support for both 8-bit and 16-bit data bus width and a UTOPIAderived packet interface with support for both 8-bit and 16-bit data bus widths.

TAAD08JU2 provides a complete ATM access function from AAL/CPS mapping functions (for AAL2 and 5) through ATM/TC/PHY layers. The highly integrated, flexible architecture results in unified OAM features, simpler operation, and best-in-class operation with respect to area, power, and function.