Features: ` 3.3 V operation
` Per-channel programmable gains, equalization,termination impedance, and hybrid balance
` Programmable m-law, linear, or A-law modes
- Up to 256 time slots per frame
- Supports PCM data rates of 512 kbits/s to 16.384 Mbits/s
- Double-clock mode timing compatible with ISDN standard interfaces
` Fully programmable time-slot assignment with bit offset
` Analog and digital loopback test modes
` Serial microprocessor interface
- Normal and byte-by-byte control modes
- Fast scan mode
` Six bidirectional control leads per channel, for SLIC and line card function control
` Differential analog output
- Mates directly to SLICs, eliminating external components
` Sigma-delta converters with dither noise reduction
` Quad design to minimize package count on dense line card applications
` Meets or exceeds ITU-T G.711-G.712 and relevant
Telcordia Technologies* requirementsPinout
Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
| Storage Temperature Range |
Tstg |
-55 |
150 |
|
| Power Supply Voltage (all leads designated power) |
VDDX |
- |
VDDX+0.5 |
V |
| Negative Voltage on Any Lead with Respect to Ground |
VSS |
-0.25 |
- |
V |
Thermal Resistance, Junction to Ambient:
64-Pin TQFP1
100-Pin TQFP1 |
RJA
RJA
|
-
-
|
40
30
|
/W
/W
|
| Package Power Dissipation |
PD |
- |
1 |
W |
| SLIC Control Interface Latches, Current per Device |
IL |
- |
160 |
mA |
1. Four layer, JEDEC test board.
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
DescriptionThe T8538A consists of four independent channels of codec and digital signal processing functions on one chip. In addition to the classic A-to-D and D-to-A conversion, each channel provides termination impedance synthesis and a hybrid balance network.
The T8538A is controlled by a serial microprocessor interface, and a series of bidirectional I/O leads are provided so that this control mechanism can be utilized to operate the battery feed device, ringing voltage switches, etc. Common data and clock paths can be shared over any number of devices. All the filter coefficients, signal processing, SLIC, and test features are accessible through this interface. This serial interface can be operated at speeds up to 16 Mbits/s.
The choice of a PCM bus is also programmable, with any channel capable of being assigned to any time slot. The PCM bus can be operated at speeds up to 16.384 Mbits/s, allowing for a maximum of 256 time slots. Separate transmit and receive interfaces are available for 4-wire bus designs, or they can be strapped together for a 2-wire PCM bus.
The device is available in two packages.
The T8538A 64-pin TQFP features five data latches per channel.
The T8538A 100-pin TQFP features six data latches per channel.
The T8538A and the T8539A Quad Programmable Line Card Signal Processor with Echo Cancellation are pin compatible.
T8538A Data Sheet
