T8502

Features:

` +5 V only
` Two independent channels
` Pin-selectable receive gain control
` Pin-selectable -law or A-law companding
` Automatic powerdown mode
` Low-power, latch-up-free CMOS technology
   - 40 mW/channel typical operating power dissipation
   - 12.5 mW/channel typical standby power dissipation
` Automatic master clock frequency selection
   - 2.048 MHz or 4.096 MHz
` Independent transmit and receive frame strobes
` 2.048 MHz or 4.096 MHz data rate
` On-chip sample and hold, autozero, and precision voltage reference
` Differential architecture for high noise immunity and power supply rejection
` Meets or exceeds ITU-T G.711-G.714 requirements and VF characteristics of D3/D4 (as per Bellcore PUB43801)
` Operating temperature range: 40°C to +85°C


Specifications

Parameter	Symbol	Min	Max	Unit
Storage Temperature Range	Tstg	55	150	°C
Power Supply Voltage	VDD	-	6.5	V
Voltage on Any Pin with Respect to Ground	-	-0.5	0.5 + VDD	V
Maximum Power Dissipation (package limit)	PD	-	600	mW

Description

The T8502 and T8503 devices are single-chip, twochannel, m-law/A-law PCM codecs with filters. These integrated circuits provide analog-to-digital and digital-to-analog conversion. They provide the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. These devices are packaged in both 20-pin SOJs and 20-pin SOGs.

The T8502 differs from the T8503 in its timing mode. The T8502 operates in the delayed timing mode (digital data is valid one clock cycle after frame sync goes high), and the T8503 operates in the nondelayed timing mode (digital data valid when frame sync goes high) (see Figures 5 and 6).