T83C5102

Features:

80C51 code Compatible
  ` 8051 instruction compatible
  ` 16 I/O + 2 Outputs in 24 pin packages
      16 I/O + 6 Outputs in 28 pin packages
  ` Three 16-bit timer/counters
  ` 256 bytes scratchpad RAM
Program Memory
  ` 8Kb ROM T83C5102
  ` 16Kb ROM T83C5101
  ` 16Kb EPROM/OTP T87C5101
High-Speed Architecture
  ` 40 MHz from 2.7 to 5.5V, commercial or industrial temperature range :
    - 40 MHz with a 40 MHz crystal in std mode
    - 40 MHz with a 20 MHz crystal in X2 mode
  ` 66 MHz from 4.5 to 5.5V, commercial temperature range
    - 40MHz with a 40 MHz crystal in std mode
    - 66MHz with a 33MHz crystal in X2 mode
Dual Data Pointer
On-chip eXpanded RAM (XRAM) (256 bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Asynchronous port reset
Interrupt Structure with
  ` 6 Interrupt sources,
  ` 4 level priority interrupt system
Full duplex Enhanced UART
  ` Framing error detection
  ` Automatic address recognition
Low EMI (no ALE)
Power Control modes
  ` Idle mode
  ` Power-down mode
Packages: SO24, DIL24, TSSOP24*, SO28*

* check for availability


Pinout




Specifications

Ambiant Temperature Under Bias:
C = commercial                             0°C to 70°C
I = industrial                                 -40°C to 85°C
Storage Temperature                   -65°C to + 150°C
Voltage on V_CC to V_SS                  -0.5 V to + 7 V
Voltage on V_PP to V_SS                  -0.5 V to + 13 V
Voltage on Any Pin to V_SS            -0.5 V to V_CC + 0.5 V
Power Dissipation                       1 W⁽²⁾

NOTES
1. Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.


Description

TEMIC T8xC5101/T83C5102 family is a high performance CMOS ROM, OTP, EPROM derivative of the 80C51 CMOS single chip 8-bit microcontroller.

The T8xC5101/T83C5102 family is a low pin count device where only Port 1, port 3 and 2/6 bits of a new port 4 are outputted. This prevents to do any external access, like external program memory access (fetch, MOVC) or external data memory (MOVX)

The T8xC5101/T83C5102 family retains all features of the TEMIC 80C51 with extended capacity 8Kb ROM (5102), 16Kb ROM (5101) / 16Kb EPROM/OTP (5101) , 256 bytes of internal RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three timer/counters.

In addition, the T8xC5101/T83C5102 family has an XRAM of 256 bytes, the X2 feature, a more versatile serial channel that facilitates multiprocessor communication (EUART), a dual data pointer and an improved timer 2.

The fully static design of the T8xC5101/T83C5102 family allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

The T8xC5101/T83C5102 family has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.