Features: ` Four fully integrated T1/E1 line interfaces` Includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions` Ultralow power consumption` Robust operation for increased system margin` High interference immunity` On-chip transmit equalization for improved s...
T7693: Features: ` Four fully integrated T1/E1 line interfaces` Includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions` Ultralow power consumption` Robust operation f...
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Parameter |
Min |
Max |
Unit |
dc Supply Voltage |
-0.5 |
6.5 |
V |
Storage Temperature |
-65 |
125 |
|
Maximum Voltage (digital pins) with Respect to VDDD |
- |
0.5 |
V |
Minimum Voltage (digital pins) with Respect to GNDD |
-0.5 |
- |
V |
Maximum Allowable Voltages (RTIP[1-4], RRING[1-4]) with Respect to VDD |
- |
0.5 |
V |
Minimum Allowable Voltages (RTIP[1-4], RRING[1-4]) with Respect to GND |
-0.5 |
- |
V |
The T7690 and T7693 are fully integrated quad line interfaces containing four transmit and receive channels for use in both North American (T1/DS1) and European (E1/CEPT) applications. The devices have many of the same functions as the Lucent Technologies Microelectronics Group T7693 and provide additional flexibility for the system designer.
Included is a parallel microprocessor interface that allows the user to define the architecture, initiate loopbacks, and monitor alarms. The T7693 interface is compatible with many commercially available microprocessors.
The receiver performs clock and data recovery using a fully integrated digital phase-locked loop. This T7693 that are common when recovering sparse data patterns with analog phase-locked loops. Equalization circuitry in the receiver guarantees a high level of interference immunity. As an option, the raw sliced data (no retiming) can be output on the receive data pins.
Transmit equalization is implemented with lowimpedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. The quad T7693 device will interface to the digital cross connect (DSX) at lengths of up to 655 ft. for DS1 operation or to line impedances of 75 or 120 for CEPT operation.
A selectable jitter attenuator may be placed in the receive signal path for low-bandwidth line-synchronous applications, or it may be placed in the transmit path for multiplexer applications where DS1/CEPT signals are demultiplexed from higher rate signals. The jitter attenuator will perform the clock smoothing required on the resulting demultiplexed gapped clock.