T54LS373

The T54LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronous) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus outputs is in the high impedance state.

There are some features of T54LS373 as follows. First is eight latches in a single package. The second is 3-state outputs for bus interfacing. Then is hysteresis on latch enable. Besides,input lamp diodes limit high speed termination effects. The last one is fully TTL and CMOS compatible.

What comes next is about the absolute maximum ratings about T54LS373. The VCC (supply voltage) is from -0.5 to 7 V. The VI (input voltage, applied to input) is from -0.5 to 15 V. The VO (output voltage, applied to output) is from -0.5 to 10 V. The II (input current, into inputs) is from -30 to 5 mA. The IO (output current, into outputs) is 50 mA. Then is about the guranteed operating ranges. The minimum supply voltage is 4.5 V, the typical is 5.0 V and the maximum is 5.5 V and the temperature is from -55 to +125.