Features: ·Organization 1048,576 word x 16bit (M5M29GB/T161BWG) ·Supply voltage ................................ VCC = 2.7~3.6V·Access time 90ns (Max.)·Power Dissipation Read 54 mW (Max. at 5MHz) (After Automatic Power saving) 0.33mW (typ.) Program/Erase 126 mW (Max.) Standby 0.33mW (typ.) Deep po...
T161BWG: Features: ·Organization 1048,576 word x 16bit (M5M29GB/T161BWG) ·Supply voltage ................................ VCC = 2.7~3.6V·Access time 90ns (Max.)·Power Dissipation Read 54 mW (Max. at 5MHz) (A...
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·Organization 1048,576 word x 16bit (M5M29GB/T161BWG)
·Supply voltage ................................ VCC = 2.7~3.6V
·Access time 90ns (Max.)
·Power Dissipation Read 54 mW (Max. at 5MHz) (After Automatic Power saving) 0.33mW (typ.) Program/Erase 126 mW (Max.) Standby 0.33mW (typ.) Deep power down mode 0.33mW (typ.)
·Auto program for Bank(I) Program Time 4ms (typ.) Program Unit (Byte Program) 1word (Page Program) 128word
·Auto program for Bank(II) Program Time 4ms (typ.) Program Unit 128word
·Auto Erase Erase time 40 ms (typ.) Erase Unit Bank(I) Boot Block 16Kword x 1 Parameter Block 16Kword x 7 Bank(II) Main Block 32Kword x 28
·Program/Erase cycles 100Kcycles
·Boot Block M5M29GB161BWG Bottom Boot M5M29GT161BWG Top Boot
·Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II)
·Package 7mm x 8.5mm CSP (Chip Scale Package) - 6 x 8 balls, 0.75mm ball pitch
The MITSUBISHI Mobile FLASH M5M29GB/T161BWG are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the M5M29GB/T161BWG simultaneously allows Read operations to be performed on the other bank. This BGO eature is suitable for mobile and personal computing, and communication products. The M5M29GB/T161BWG are fabricated by CMOS echnology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 6x8-balls SP (0.75mm ball pitch) .