SiI 2022

General
• Fibre Channel-compliant
• Multi-rate: 1.0625 Gbps and 2.125 Gbps

Low Power
• Single 3.3V supply for core circuits and high-speed I/O
• Power dissipation: 450 mW

Cost Effective
• Standard CMOS technology
• Compact 64-pin, 14x14mm MQFP (Metric Quad Flat Pack)

Narrow Parallel I/O
Interface
• 10-bit interface with DDR for 2.125 Gbps mode
• SSTL_2 and High-Speed Parallel Interface (HSPI)-compliant
• Separate transmit byte clock (TBC) for latching parallel input data

Highly Reliable Serial
Interface
• Separately selectable Tx and Rx data rates
• Very-low-jitter PLL: 3.3 ps (random jitter), 32 ps (deterministic jitter)
• Variable pre-emphasis control
• Variable on-chip termination resistor
• Full ESD tolerance to 2 kV

Proven Technology
• MSLTM-based technology proven with PanelLink^® ICs for the PC and CE markets (2-5 Gbps, over 30M units shipped)
• Robust design for "noisy" environments

Silicon Image's SiI 2022 serializer/deserializer (SerDes) is capable of transmitting and receiving data at 1.0625 and 2.125 gigabits-per-second (Gbps). Targeted at Fibre Channel applications, the SiI 2022 SerDes is designed for power, performance and price. Making use of a robust, CMOS design that significantly reduces power dissipation and jitter, the SiI 2022 provides a low-cost solution for applications that require a high-performance Fibre Channel SerDes. Available in a 64-pin, 14x14 mm MQFP package, the SiI 2022 supports selectable transmit and receive data rates for automatic speed negotiation and a narrow 10-bit SSTL_2-compatible interface for parallel data input/output.

The SiI 2022 SerDes leverages much of the circuit innovation at the physical layer of Silicon Image's proprietary reduced overhead Multi-layer Serial Link (MSLTM) architecture, pioneered and proven through the company's market-leading PanelLink® products. MSL technology is a multi-layer approach to providing robust, cost-effective, multi-gigabit semiconductor solutions on a single chip for high-bandwidth applications.