Si3909DV

The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model Si3909DV is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance of Si3909DV is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values of Si3909DV are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.