Features: ` Complies with PCI Rev. 2.2 specification
` Supports Ultra3 DT clocking for data transfers up to 160 Mbytes/s per channel
` Supports enhanced protection on nondata asynchronous phases through AIP
` Supports CRC checking and generation in DT phases
` Supports Domain Validation
Basic (level 1) with Inquiry Command (Inquiry Check)
Enhanced (level 2) with Read/Write Buffer
Margined (level 3) with margining of LVD drivers and programmable skew test
` All cycles to SCRIPTS RAM stay internal to the device, not generating PCI cycles
` SCRIPTS engine with improved instruction fetch performanceSpecifications
| Symbol |
Parameter |
Min |
Max1 |
Unit |
Test Conditions |
| TSTG |
Storage temperature |
-55 |
150 |
°C |
|
| VDD |
Supply voltage |
-0.5 |
4.5 |
V |
|
| VIN |
Input voltage |
-0.3 |
5.55 |
V |
|
| VIN-PCI |
Input voltage PCI pins |
-5 |
11.0 |
V |
|
| ILP 2 |
Latch-up current |
±150 |
|
mA |
|
| T |
Lead temperature |
|
250 |
°C |
< 10 seconds |
| ESD3 |
Electrostatic discharge |
|
2K |
V |
MIL-STD 883C,
Method 3015.7 |
1. Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied.
2. -2 V < VPIN < 8 V.
3. SCSI pins only.
DescriptionThe SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller brings Ultra3 SCSI performance to host adapter, workstation, and server designs, making it easy to add a high-performance SCSI bus to any PCI system.
The SYM53C1010-33 is pin and software compatible with the SYM53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller, thus making migration easy (pin compatible means that the SYM53C896 can operate in an SYM53C1010 socket but the SYM53C1010-33 cannot operate in an SYM53C896 socket). The SYM53C1010 supports a 64-bit or 32-bit, 33 MHz PCI bus. The Ultra3 SCSI features in the SYM53C1010 are: Double Transition (DT) clocking, Cyclic Redundancy Check (CRC), and Domain Validation. These features comply with the Ultra160 SCSI industry initiative.
DT clocking permits the SYM53C1010-33 to transfer data up to 160 megabytes per second (Mbytes/s) on each channel for a total of 320Mbytes/s. CRC improves the integrity of the SCSI data transmission through enhanced detection of communication errors. Asynchronous Information Protection (AIP) augments CRC to protect all nondata phases, providing complete end-to-end protection of the SCSI I/O. SURElink™ Domain Validation detects the SCSI bus configuration and automatically tests and adjusts the SCSI transfer rate to optimize interoperability. Three levels of Domain Validation are provided, assuring robust system operation.
The SYM53C1010-33 has a local memory bus. This allows local storage of the device's BIOS ROM in flash memory or standard EPROMs. The SYM53C1010 supports programming of local flash memory for BIOS updates. The chip is packaged in a 329 Ball Grid Array (BGA). Figure 1.1 shows a typical SYM53C1010-33 board application connected to external ROM or flash memory.
SYM53C1010-33 Data Sheet
