SY89113U

Features: • Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies• Guaranteed AC performance over temperature and voltage: DC to >1GHz throughput <975ps propagation delay CLK0-to-Q <250ps rise/fall time <25ps output-to-output skew• Ultr...

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SeekIC No. : 004510302 Detail

SY89113U: Features: • Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies• Guaranteed AC performance over temperature and voltage: DC to >1GHz throughput <9...

floor Price/Ceiling Price

Part Number:
SY89113U
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

• Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies
• Guaranteed AC performance over temperature and voltage:
DC to >1GHz throughput
<975ps propagation delay CLK0-to-Q
<250ps rise/fall time
<25ps output-to-output skew
• Ultra-low jitter design:
<1psRMS random jitter
<10psPP total jitter (clock)
<1psRMS cycle-to-cycle jitter
<0.7psRMS crosstalk induced jitter
• Unique, patent-pending 2:1 input MUX provides superior isolation to minimize channel-to-channel crosstalk
• CLK0 input features a unique, patent-pending input termination and VT pin that accepts AC- and DCcoupled
inputs (CML, LVPECL, LVDS)
• CLK1 accepts virtually any logic standard:
Single-ended: TTL/CMOS (including 3.3V logic), LVPECL
Differential: LVPECL, LVDS, CML, HSTL
• 325mV LVDS-compatible output swing
• Power supply: 2.5V +5%
• Industrial temperature range 40°C to +85°C
• Available in 44-pin (7mm x 7mm) MLF™ package





Application

• Multi-processor server
• SONET/SDH clock/data distribution
• Fibre Channel distribution
• Gigabit Ethernet clock distribution





Pinout

  Connection Diagram




Specifications

Supply Voltage (VCC) ........................ 0.5V to +4.0V
Input Voltage
(Differential Input CLK0, CLK1(4, 5)).. 0.5V to VCC
Current on Reference Voltage Outputs
Source or sink current on VREF-AC0, VBB1......±2mA
Termination Current
Source or sink current on VT0.....................±100mA
Input Current
Source or sink current on CLK0, /CLK0 .........±50mA
Lead Temperature (soldering, 20 sec.) ......... +260°C
Storage Temperature (Ts) ............. 65°C to 150°C
4. SE-TERM not connected.
5. Using single-ended TTL/CMOS input signals, SE-TERM connects to GND. See Figure 4f.





Description

LVDS fanout buffer optimized for precision telecom and enterprise server distribution applications. The input includes a 2:1 MUX for clock switchover applications. Unlike other multiplexers, this input includes a unique isolation design that minimizes channel-to-channel crosstalk. The SY89113U distributes clock frequencies from DC to >1GHz guaranteed over temperature and voltage. The SY89113U incorporates a synchronous output enable (EN) so that the outputs will only be enabled/disabled when they are already in the LOW state. CLK0 differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. CLK1 differential input includes a new version of Micrel's unique, Any-Input architecture that directly interfaces with single-ended TTL/CMOS logic (including 3.3V logic), single-ended LVPECL, differential (AC- or DC-coupled) LVDS, HSTL, CML, and LVPECL logic levels as small as 200mV (400mVPP). CLK1 input requires external termination. LVDS output swing 325mV into 100 with extremely fast rise/fall time guaranteed to be less than 250ps.

The SY89113U operates from a 2.5V±5% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89113U is part of Micrel's high-speed, Precision Edge® product line. All support documentation can be found on Micrel's web site at: www.micrel.com.






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