SX52BD

Maximum Clock Frequency :
Program Memory Size :
Data RAM Size :
On-Chip ADC :
Operating Supply Voltage :
Operating Temperature Range :
Package / Case :
Mounting Style :
Processor Series :
Data Bus Width : 8 bit
Core : RISC


Features:

• 75 MIPS Performance
• DC - 75 MHz operation
• 13.3 ns instruction cycle, 39.9 ns internal interrupt response at 75 MHz
• 1 instruction per clock (branches 3) EE/FLASH Program Memory ad SRAM Data Memory
• Access time of < 13.3 ns provides single cycle access
• EE/Flash rated for > 10,000 rewrite cycles
• 4096 Words of EE/Flash program memory
• 262x8 bits SRAM data memory
• CPU Features
• Compact instruction set
• All instructions are single cycle except branch
• Eight-level push/pop hardware stack for subroutine
• linkage
• Fast table lookup capability through run-time readable code (IREAD instruction)
• Predictable program execution flow for hard real-time applications


Pinout

Specifications

Ambient temperature under bias	-40°C to +85°C
Storage temperature	-65°C to +150°C
Voltage on Vdd with respect to Vss	0 V to +7.0V
Voltage on OSC1 with respect to Vss	0 V to +13.5V
Voltage on MCLR with respect to Vss	0 V to +13.5V
Voltage on all other pins with respect to Vss	-0.6 V to (Vdd + 0.6V)V
Total power dissipation	1 W at 70°C 1.5 W at 25°C
Max. current out of Vss pin	180 mA at 70°C 300 mA at 25°C
Max. current into Vdd pin	180 mA at 70°C 300 mA at 25°C
Max. DC current into an input pin (with internal protection diode forward biased)	±500 mA
Input clamp current, Iik (Vi < 0 or Vi > Vdd)	±20 mA
Output clamp current, lok (VO < 0 or VO > Vdd)	±20 mA
Max. allowable sink current per I/O pin	45 mA
Max. allowable source current per I/O pin	45 mA
Max. allowable sink current per group of I/O pins between Vdd pins	50 mA
Max. allowable source current per group of I/O pins between Vdd pins	50 mA
Latchup	200 mA
JA, 48-pin Package	85°C/W
JA, 52-pin Package	82°C/W
Number of EEPROM Write Cycles	10,000
ESD Human Body Model - all pins	2000V
ESD Machine Model - all pins	200V

Description

The SX52BD contains five 8-bit I/O ports (Port A through Port E). Port A provides symmetrical drive capability. In the 48-pin version of the SX52BD, Port A has only four pins rather than eight. The unavailable pins are pulled high. Each port has four associated 8-bit registers (Direction, Data, TTL/CMOS Select, and Pull-Up Enable) to configure each port pin as Hi-Z input or output, to select TTL or CMOS voltage levels, and to enable/disable the weakpull-up resistor. The least significant bit of the  registers corresponds to the least significant port pin. To access these configuration registers, an appropriate value must be written into the MODE register

SX52BD also supports the on-chip differential comparator. Ports RB1 and RB2 are the comparator negative and positive inputs, respectively, while Port RB0 is the comparator output pin. Port B also supports the Multi-Input  Wakeup feature on all eight pins.

SX52BD also support the multi-function timers T1 and T2. RB4 and RB5 are the T1 capture inputs, RB6 is the T1 PWM output, and RB7 is the T1 external event counter input. Similarly, RC0 and RC1 are the T2 capture inputs, RC2 is the T2 PWM output, and RC3 is the T2 external event counter input.

Parameters:

Technical/Catalog Information	SX52BD
Vendor	Parallax Inc
Category	Integrated Circuits (ICs)
Program Memory Size	6KB (4K x 12)
RAM Size	262 x 8
Number of I /O	40
Package / Case	52-QFP
Speed	50MHz
Controller Series	SX
Oscillator Type	Internal
Packaging	Tray
Program Memory Type	FLASH
EEPROM Size	-
Core Processor	RISC
Data Converters	-
Core Size	8-Bit
Operating Temperature	0°C ~ 70°C
Connectivity	-
Peripherals	-
Voltage - Supply (Vcc/Vdd)	-
Drawing Number	*
Other Names	SX52BD SX52BD