STEL1108

· Complete BPSK/DBPSK/QPSK/DQPSK modulator in a CMOS ASIC
· Operates at up to 6.3 Mbps in BPSK mode and up to 12.6 Mbps in QPSK mode.
· Programmable over a wide range of data rates
· NCO modulator provides fine frequency resolution
· 126 MHz maximum clock rate generates modulated carrier at frequencies to 50 MHz
· Eliminates most analog circuitry
· Operates in continuous and burst mode
· Selectable 10- or 12-bit outputs
· 32-tap FIR filter for signal shaping before modulation
· 80-Pin MQFP Package

The timing of the STEL-1108 is controlled by the Clock Generator Block. This block generates all the clocks required in the device from the CLK input, as well as the output clocks. The divider which determines the bit rate, symbol rate and sampling rate of the FIR filter is programmed by the data "n" written into address 29H, with the sampling frequency set to fCLK/(n+1), where n can be from 4 to 255. A second divider is used to generate the auxiliary output clock (ACLKOUT) from the clock input. This divider is controlled by the data, "n", stored in bit 3-0 in address 2AH, with the frequency set to fCLK/(n+1), where n can be from 2 to 15. Of all the clock signals generated, only the auxiliary clock continues to run when the clock enable is low. The bit clock output runs at twice the symbol rate, even in BPSK mode.

Input Data Processor Block

The STEL-1108 is designed to operate as a BPSK, QPSK, DBPSK or DQPSK modulator according to the setting of bit 3 in address 2CH and the DIFFEN input. When operating in QPSK mode the input data processor assembles pairs of data bits for each symbol to be modulated. The symbol data can then be differentially encoded in a way which depends on whether the modulation format is to be DBPSK or DQPSK. For
DBPSK, the encoding algorithm is straightforward:
output bit(k) = input bit(k)   output bit(k1),
where   represents the logical EXOR function. ForDQPSK, however, the differential encoding algorithm is more complex since there are now sixteen possible new states depending on the four possible previous output states and four possible new input states, as shown in the table below:
New Input Previously Encoded OUT(I, Q)_k1
IN(I, Q)_k 0 0 0 1 1 1 1 0
     0 0     0 0 0 1 1 1 1 0
     0 1     0 1 1 1 1 0 0 0
     1 1     1 1 1 0 0 0 0 1
     1 0     1 0 0 0 0 1 1 1
                Newly Encoded OUT(I, Q)k

FIR Filter Block

The encoded data is filtered to minimize the sidelobes of its spectrum using a 32-tap, linear phase FIR filter. The 10-bit filter coefficients are completely programmable for any symmetrical (mirror image) polynomial and are stored in the registers at addresses 09H to 28H, giving the user full control (apart from the symmetry constraint) of the filter response. The clock (sampling) frequency of the FIR filter is set to be four times the symbol rate. This frequency is determined by the data, "n", written into address 29H, with the sampling frequency set to fCLK/(n+1), where n can be from 4 to 255.

Interpolating Filter Block

The output of the FIR filter is interpolated up to the clock frequency, fCLK, in a one, two or three stage interpolating filter. Since the gain of the integrators in the interpolating filter can vary over a wide range, a gain control function is provided at its input to select the significance of the 14-bit outputs of the FIR filter relative to the 24-bit inputs of the interpolating filter. This level shift function is controlled by the data stored in bit 7-4 in address 2AH.

Frequency Control Word Buffer Block

The STEL-1108 incorporates a Numerically Controlled Oscillator (NCO) to synthesize the carrier in the modulator. The frequency of the NCO is programmed by means of the Frequency Control Word (FCW) registers at addresses 00H through 08H. The STEL-1108 incorporates provision for three separate FCWs (FCW A, FCW B and FCW C) to be stored in these registers. The modulator frequency can be switched between these values by means of the FCWSEL1-0 inputs. The fourth setting of this 2-bit input selects a zero-frequency value, causing the modulator output to stop instantly at its current phase.

Phase Accumulator and Sine/Cosine Lookup Table Block

The 24-bit NCO gives a frequency resolution of approximately 6 Hz at a clock frequency of 100 MHz. The 12-bit sine and cosine lookup tables (LUTs) synthesize a carrier with very high spectral purity, typically better than 75 dBc at the digital outputs.

Complex Modulator Block

The interpolated I and Q data signals are fed into the Complex Modulator Block to be multiplied by the sine and cosine carriers from the Sin/Cos LUT Block.

Adder Block

The modulated sine and cosine carriers are fed into the Adder Block where they are either added or subtracted together to form the sum:

Sum = ± I . cos(wt) ± Q . sin(wt)

The signs of the I and Q components can be controlled by the settings of bits 0 and 1 in address 2BH, giving complete control over the characteristics of the RF signal generated.