Features: Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes
0-25 MHz Operation (internal clock) @ 5V±10% voltage range
-40°C to +85°C Operating Temperature Range
Fully Programmable PLL Clock Generator, with Frequency Multiplication and low frequency, low cost external crystal (3-5 MHz)
Minimum Instruction Cycle time: 160 ns - (@ 25 MHz internal clock frequency)
Internal Memory:
EPROM/OTP/FASTROM 16K bytes
RAM 512 bytes
224 general purpose registers available as RAM, accumulators or index pointers (register file)
32-pin Dual Inline and 34-pin Small Outline Packages
15 programmable I/O pins with Schmitt Trigger input, including 4 high sink outputs (20mA @ VOL=3V)
4 Wake-up Interrupts (one usable as Non- Maskable Interrupt) for emergency event management
3-phase Induction Motor Controller (IMC) Peripheral with 3 pairs of PWM outputs and asynchronous emergency stop
Serial Peripheral Interface (SPI) with Master/ Slave Mode capability
16-bit Timer with 8-bit Prescaler usable as a Watchdog Timer
16-bit Standard Timer with 8-bit Prescaler
16-bit Extended Function Timer with Prescaler, 2 Input Captures and 2 Output Compares
8-bit Analog to Digital Converter allowing up to 6 input channels with autoscan and watchdog capability
Low Voltage Detector Reset
Rich Instruction Set with 14 Addressing Modes
Division-by-Zero trap generation
Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating System available from Third PartiesPinout
Specifications
|
Symbol |
Parameter |
Value |
Unit |
|
VDD |
Supply Voltage |
0.3 to 6.5 |
V |
|
AVDD |
A/D Converter Analog Reference |
up to VDD + 0.3 (1) |
V |
|
AVSS |
A/D Converter VSS |
VSS |
|
|
VIN |
Input Voltage (standard I/O pins) |
0.3 to VDD + 0.3 |
V |
|
VAIN |
Analog Input Voltage (A/D Converter) |
AVSS to AVDD |
V |
|
ESD |
ESD susceptibility |
2000 |
V |
|
TSTG |
Storage Temperature |
55 to +150 |
°C |
|
IINJ |
Pin Injection Current - Digital and Analog Input |
+/- 10 |
mA |
| |
Maximum Accumulated Pin Injection Current |
+/- 100 |
mA |
Note:
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to VSS=0.
(1) AVDD can be shut down while the A/D Converter is not in use.Description1.1 INTRODUCTION
The ST92141 microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the ST92141 (CPU), the Register File, the Interrupt controller, and the Memory Management Unit. The MMU allows addressing of up to 4 Megabytes of program and data mapped into a single linear space.
Four ST92141 independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt bus which connects the interrupt controllers in the on-chip peripherals with the core.
Note: The DMA features of the ST9+ core are not used by the on-chip peripherals of the ST92141.
This multiple bus architecture makes the ST92141 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as accumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST92141 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/ register and memory/memory exchanges.
1.1.2 Power Saving Modes
To optimize performance versus power consumption, a range of operating modes can be dynamically selected by software according to the requirements of the application.
Run Mode. This is the full speed execution mode with ST92141 and peripherals running at the maximum clock speed delivered either by the Phase Locked Loop controlled by the RCCU (Reset and Clock Control Unit), directly by the oscillator or by an external source (dedicated Pin or Alternate Function).
Slow Mode. Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the ST92141 Prescaler and RCCU Clock Divider.
Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the ST92141 clock is halted while the peripheral with interrupt capability and interrupt controller are kept running at a frequency that can be programmed by software in the RCCU registers. In this mode, the power consumption of the device can be reduced by more than 95% (Low Power WFI).
Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the ST92141 and its peripherals stop operating. If however the Watchdog is enabled, the HALT instruction has no effect. The main difference between Halt mode and Stop mode is that a reset is necessary to exit from Halt mode which causes the system to be reinitialized.
Stop Mode. When Stop mode is requested by executing the STOP sequence (see Wake-up Management Unit section), the ST92141 CPU and the peripherals stop operating. Operations resume after a wake-up line is activated. The difference between Stop mode and Halt mode is in the way the CPU exits each state: when the STOP sequence is executed, the status of the registers is recorded, and when the system exits from Stop mode the CPU continues execution with the same status, without a system reset.
The Watchdog counter, if enabled, is stopped. After exiting Stop mode it restarts counting from where it left off.
When the ST92141 MCU exits from STOP mode, the oscillator, which was also sleeping, requires a start-up time to restart working properly. An internal counter is present to guarantee that, after exiting Stop Mode, all operations take place with the clock stabilised.
1.1.3 System Clock
A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 25MHz.
ST92141 Data Sheet
