ST90R28

The ST90R28 has the following features including Registeroriented 8/16 bit COREwith RUN. WFI and HALT modes;Minimum instruction cycle time:500ns(12MHz internal);ROMless to allow maximum external memoryflexibility;Internal Memory:RAM 256 bytes,224 general purpose registers available as RAM, accumulators or index pointers(register file);56-pin Plastic Dual-In-Line package;DMA controller, Interrupt handler and Serial Peripheral interface as standard features;40 fully programmable I/O pins.

The ST90R28 is a ROMLESS member of the ST9 family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process.The ROMLESS part may be used forthe prototyping and pre-production phases of development,and offers the maximum in program flexibility in production systems.The ST90R28 is fully compatible with the ST902x ROM version and this datasheet will thus provide only information specific to the ROMLESS device.The ROMLESS ST90R28 can be configured as a microcontroller able to manage external memory, or as a parallel processing element in a system with other processors and peripheral controllers.The nucleus of the ST90 R28 is the advanced Core which includes the Central Processing Unit (CPU),the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaler a Serial Peripheral Interfacesupport-ing S-BUS, IBC-bus and IM-bus Interface, plus two 8 bit I/O ports. The Core has independentmemory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set.

Memorymay optionallybe divided into two spaces,each having a maximum of 65,536 bytes. The two memory spaces are separated by function, one space for Program code, the other for Data. The ST90R28 addresses all program memory in the external PROGRAM space. The DATA space includes the 256 bytes of on-chip RAM memory at memory addresses OOh through OOFFh.The External Memory spaces are addressed using the multiplexed address and data buses on Ports 0 and 1 .Additional Data Memorv may be decoded externaiiyoy usmgtne riuiternate runcuon output. The on-chip general purpose (GP) Registers may be used as RAM memory.