SST34HF32A4

Features: • Flash Organization: 2M x16 or 4M x8• Dual-Bank Architecture for Concurrent Read/Write Operation 32 Mbit Top Sector Protection 32 Mbit: 8 Mbit + 24Mbit• PSRAM Organization: 16 Mbit: 1024K x16• Single 2.7-3.3V Read and Write Operations• Superior Reliability ...

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SST34HF32A4 Picture
SeekIC No. : 004505293 Detail

SST34HF32A4: Features: • Flash Organization: 2M x16 or 4M x8• Dual-Bank Architecture for Concurrent Read/Write Operation 32 Mbit Top Sector Protection 32 Mbit: 8 Mbit + 24Mbit• PSRAM Organizati...

floor Price/Ceiling Price

Part Number:
SST34HF32A4
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

• Flash Organization: 2M x16 or 4M x8
• Dual-Bank Architecture for Concurrent Read/Write Operation
32 Mbit Top Sector Protection
32 Mbit: 8 Mbit + 24Mbit
• PSRAM Organization:
16 Mbit: 1024K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption:
Active Current: 25 mA (typical)
Standby Current: 70 A (typical)
• Hardware Sector Protection (WP#)
Protects 8 KWord in the smaller bank by holding WP# low and unprotects by holding WP# high
• Hardware Reset Pin (RST#)
Resets the internal state machine to reading data array
• Byte Selection for Flash (CIOF pin)
Selects 8-bit or 16-bit mode (56-ball package only)
• Sector-Erase Capability
Uniform 2 KWord sectors
• Flash Chip-Erase Capability
• Block-Erase Capability
Uniform 32 KWord blocks
• Erase-Suspend / Erase-Resume Capabilities
• Read Access Time
Flash: 70 ns
PSRAM: 70 ns
• Security ID Feature
SST: 128 bits
User: 256 bits
• Latched Address and Data
• Fast Erase and Program (typical):
Sector-Erase Time: 18 ms
Block-Erase Time: 18 ms
Chip-Erase Time: 35 ms
Program Time: 7 s
• Automatic Write Timing
Internal VPP Generation
• End-of-Write Detection
Toggle Bit
Data# Polling
Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Packages Available
56-ball LFBGA (8mm x 10mm)
62-ball LFBGA (8mm x 10mm)
• All non-Pb (lead-free) devices are RoHS compliant



Specifications

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .  . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . .  -1.0V to VDD1+1.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .260°C for 10 seconds
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA



Description

The SST34HF32A4 ComboMemory devices integrate either a 2M x16 or 4M x8 CMOS flash memory bank with 1024K x16 CMOS pseudo SRAM (PSRAM) memory bank in a multi-chip package (MCP). These devices are fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF32A4 devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system.

The SST34HF32A4 feature dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the PSRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 8 Mbit and 24 Mbit with top sector protection options for storing boot code, program code, configuration/parameter data and user data.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF32A4 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Program time of 7 sec. The entire flash memory bank can be erased and programmed word-by-word in typically 4 seconds for the SST34HF32A4, when using interface features such as Toggle Bit, Data# Polling, or RY/BY# to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF32A4 devices contain onchip hardware and software data protection schemes.

The flash and PSRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The PSRAM bank enable signals, BES1# and BES2, select the PSRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area.

Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF32A4 are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 3 for pin assignments




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