SN75LVDS83

The SN75LVDS83 FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7* clock synthesizer, differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7*) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.The SN75LVDS83 requires no external components and little or no control. The data bus appears the same at the input to the transmitter SN75LVDS83 and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers to a low level.

The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0 to 70