SN74HC595

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) (see Note 1) . . . . . . . . . . . . . . . . . . . . .±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) (see Note 1) . . . . . . . . . . . . . . . . . .±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V_CC or G_ND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, _JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 73°C/W
                                                        DB package  . . . . . . . .  . . . . . .  . . . . . . . . . . . . .82°C/W
                                                        DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57°C/W
                                                        N package . . . . . . . . . . . .. . .  . . . . . . . . . . . . . . 67°C/W
                                                        NS package . . .. . . . . . . . . . . . . . . . . . . . . . . . . .64°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

The SN74HC595 devices contain an 8-bit serial-in,parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input of the SN74HC595 is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered.If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.