SN54/74LS92

The LS90, LS92, and LS93 are 4-bit ripple type Decade, Divide-By-Twelve, and Binary Counters respectively. Each LS90, LS92, and LS93  device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight LS93) section. Each section of LS90, LS92, and LS93   has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q₀ output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device.

A gated AND asynchronous Master Reset (MR1 • MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS1 • MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH).Since the output from the divide-by-two section is not internally connected to the succeeding stages, the LS90, LS92, and LS93   devices may be operated in various counting modes.