SN54/74LS293

The LS290 and LS293 are 4-bit ripple type Decade, and 4-Bit Binary counters respectively. Each device consists of four master/ slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS290) or divide-by-eight (LS293) section. Each section of LS290 and LS293  has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device.

A gated AND asynchronous Master Reset (MR1 V MR2) is provided on both counters which overrides the clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS1 V MS2) is provided on the LS290 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH).Since the output from the divide-by-two section is not internally connected to the succeeding stages, the LS290 and LS293  devices may be operated in various counting modes: