PinoutSpecifications C31 'LC31Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . .. . . . . . 0.3 V to 7 V . . . . . . 0.3 V to 5 VInput voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . ......... . . . . . 0.3 V to 7 V . . . . . .. 0.3 V to 5 VOutput voltage, VO . . . . . . ...
SMJ320C31: PinoutSpecifications C31 'LC31Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . .. . . . . . 0.3 V to 7 V . . . . . . 0.3 V to 5 VInput voltage, VI . . . . . . . . . . . . . . . . . . ....
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SpecificationsSupply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-mm triple-level-metal CMOS technology. The devices are part of the SMJ320C3x generation of DSPs from Texas Instruments.
The SMJ320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 50 MFLOPS. The SMJ320C3x optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
The SMJ320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.
SMJ320C31 General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SMJ320C3x supports a wide variety of system applications from host processor to dedicated coprocessor.
High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.