SLK2721

PinoutSpecificationsSupply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .0.3 to 3 VVoltage range: TTL input terminals . . . . . . . . . . . . . . . . . . . . . .0.3 to 4 VLVDS terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 t...

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SLK2721 Picture
SeekIC No. : 004493240 Detail

SLK2721: PinoutSpecificationsSupply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .0.3 to 3 VVoltage range: TTL input terminals . . . . . . . . . . . . . . . . . . . . . .0.3 ...

floor Price/Ceiling Price

Part Number:
SLK2721
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Pinout

  Connection Diagram


Specifications

Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .  0.3 to 3 V
Voltage range: TTL input terminals . . . . . . . . . . . . . . . . . . . . . . 0.3 to 4 V
LVDS terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 to 3 V
Any other terminal except above . . . . . . . . . . . . . . . .  0.3 to VDD + 0.3 V
Package power dissipation, PD . . . . . . . . . . . See Dissipation Rating Table
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM: 2 kv
Characterized free-air operating temperature range, TA . . 40°C to 85°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . .260°C



Description

The SLK2721 device is a single chip, multirate transceiver that derives high-speed timing signals for SONET/ SDH-based equipment. The device performs clock and data recovery, serial-to-parallel/parallel-to-serial conversion, and a frame detection function conforming to the SONET/SDH standards.

The device SLK2721 can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rate through the rate selection pins or the autorate detection function. An external reference clock operating at 622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions.

The SLK2721 device accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at the OC-3, OC-12, OC-24, or OC-48 data rate. It also recovers the data and clock from the serial SONET stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL-compatible differential interface.

The SLK2721 device supports an FEC data rate up to 2.7 Gbps when configured to operate at the OC-48 data rate and provided with an external reference clock that is properly scaled.

The SLK2721 device provides a comprehensive suite of built-in tests for self-test purposes including local and remote loopback and pseudorandom bit stream (PRBS) (27-1) generation and verification.

The device SLK2721 comes in a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on the control pins. The SLK2721 device is very power efficient, dissipating less than 900 mW at 2.488 Gbps, the OC-48 data rate. It is characterised for operation from −40°C to 85°C.




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