Features: · Fully Integrated SONET/SDH Transceiver to
· Hot Plug Protection
Support Clock/Data Recovery and
· Low Jitter PECL Compatible Differential Serial
Multiplexer/Demultiplexer Functions Interface With Programmable De-Emphasis for
· Supports OC-48, OC-24, OC-12, Gigabit the Serial Output
Ethernet, and OC-3 Data Rate With Autorate
· On-Chip Termination for LVDS and PECL
Detection Compatible Interface
· Supports Transmit Only, Receiver Only,
· Receiver Differential Input Thresholds 150 mV
Transceiver and Repeater Functions in a Min Single Chip Through Configuration Pins
· Supports SONET Loop Timing
· Supports SONET/SDH Frame Detection
· Low Power CMOS
· On-Chip PRBS Generation and Verification
· ESD Protection >2 kV
· Supports 4-Bit LVDS (OIF99.102) Electrical
· 155-MHz or 622-MHz Reference Clock Interface
· Maintains Clock Output in Absence of Data
· Parity Checking and Generation for the LVDS Interface
· Local and Remote Loopback
· Single 2.5-V Power Supply
· 100-Pin PZP Package With PowerPAD™
Design With 5-mm×5-mm (Typ) Heatsink
· Interfaces to Back Plane, Copper Cables, or Optical Modules
Pinout
Specifications
| |
UALUE |
UNIT |
| VDD Supply voltage |
0.3 to 3 |
V |
| Voltage range |
TTL input terminals |
0.3 to 4 |
V |
| LVDS terminals |
0.3 to 3 |
V |
| Any other terminal except aboven |
0.3 to VDD + 0.3 |
V |
| PD Package power dissipation |
See Dissipation Rating Table |
| Tstg Storage temperature |
65 to 150 |
|
| Electrostatic discharge |
HBM: 2 kv |
|
| TA Characterized free-air operating temperature range |
40 to 85 |
|
| Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds |
260 |
|
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.DescriptionThe SLK2511B is a single chip multirate transceiver IC used to derive high-speed timing signals for SONET/SDH based equipment. The chip performs clock and data recovery, serial-to-parallel/parallel-to-serial conversion and frame detection function conforming to the SONET/SDH standards.
The device SLK2511B can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rates through the rate selection pins or the autorate detection function. An external reference clock operating at 155.52 MHz or 622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions.
The SLK2511B accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at OC-3, OC-12, OC-24, or OC-48 rates. It also recovers the data and clock from the serial SONET stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL compatible differential interface.
The SLK2511B provides a comprehensive suite of built-in tests for self-test purposes including local and remote loopback and PRBS (27-1) generation and verification.
The device SLK2511B comes in a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on the control pins. The SLK2511B is power efficient, dissipating less than 900 mW at 2.488 Gbps, the OC-48 data rate, and it is characterised for operation from 40°C to 85°C.
SLK2511B Data Sheet
