SDA 9064-5

Features: · Pipeline processor structure controls deflection stages· Raster alignment by keyboard or automatically· Adaptable beam current compensation for picture height and width· Protection input stops the exceeding· For double the line frequency and 100-/120-Hz vertical frequency interlacedPin...

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SDA 9064-5 Picture
SeekIC No. : 004486812 Detail

SDA 9064-5: Features: · Pipeline processor structure controls deflection stages· Raster alignment by keyboard or automatically· Adaptable beam current compensation for picture height and width· Protection input...

floor Price/Ceiling Price

Part Number:
SDA 9064-5
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

·  Pipeline processor structure controls deflection stages
·  Raster alignment by keyboard or automatically
·  Adaptable beam current compensation for picture height and width
·  Protection input stops the exceeding
·  For double the line frequency and 100-/120-Hz vertical frequency interlaced




Pinout

  Connection Diagram


Specifications

Parameter Symbol Limit Values Unit
min. max.
Input voltage VIM 0.5 6.0 V
Supply voltage VDD 0.3 6.0 V
Substrate voltage VSUB 3.2 0 V
Total power dissipation Ptot   1.7 W
Ambient temperature range TA 0 70 °C
Storage temperature range Tstg 55 125 °C
Thermal resistance
system-air
Rth SA   36 K/W


 




Description

The DDC SDA 9064-5 consists essentially of a processor with program ROM and RAM, ports for input and output signals and a clock rate divider that supplies the whole chip with clock signals.

The processor is specially manufactured for the arithmetic operations performed in the DDC. SDA 9064-5 operates according to the pipeline principle on account of the high requirements involved with regard to time. SDA 9064-5 has two 16-bit accumulators. The 16-bit data bus and the 7-bit address bus take care of the data traffic between the processor and the ports. The size of the static RAM is 96 x 16 bits; the program ROM can store 800 16-bit instructions.

The V port and the 2 port of SDA 9064-5 comprise counters for coarse conversion and a chain of 32 resistors for amplitute quantization of fine conversion. The 2 port further measures the position of the ZR pulses with respect to time and transfers measured data to the processor. The east/west port similarly of SDA 9064-5 has a counter for digital time conversion but manages without fine conversion.

The 9-bit analog-to-digital converter SDA 9064-5 works on the principle of successive approximation using a capacitance field.

The I2C Bus SDA 9064-5 interface makes it possible to read and modify deflection data in the RAM. The protective circuitry monitors inputs SS, ZR and HA2EN using comparators.

The start-up circuitry of SDA 9064-5 has its own power and clock pulse supply. It is therefore completely independent of the other DDC functions.


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