SDA 4330-2X

The SDA 4330-2X is a radio PLL controlled via I2C Bus for frequency synthesis in the AM and FM range. It includes an IF counter up to 50 MHz enabling a precise search tuning stop.

The reference frequency for the PLL is derived from the quartz oscillator OSC1). The R-prescaler of SDA 4330-2X can be adapted to quartz frequencies of 4, 8 or 10.25 MHz, respectively, yielding an internal 50 kHz reference. Programming the R-counter sets the phase detector reference frequency to 1, 5 or 10 kHz in the AM mode or to 12.5, 25 or 50 kHz in the FM mode. The VCO frequency of SDA 4330-2X is set by programming the A/N-counter which operates as dual-modulus counter for FM and AM using a divide by 4/5 swallow counter.

The phase detector drives two different charge pumps for AM and FM mode. Additional source followers of SDA 4330-2X are connected to the charge pump. There are four programmable current levels for each charge pump. The supply voltage of SDA 4330-2X for the charge pump and the source followers is supplied via the VDD2-pin and can reach 10 V maximum. AM/FM is an open drain output as well as the additional outputs SA1 . SA4 which are controlled by I2C Bus.

The IF counter of SDA 4330-2X is activated by the IF bit of the I2C status word. In the FM mode the IFFM signal is divided by 2 or 4 in the F-counter in the AM mode the IFAM input is switched directly to the gate. The G-counter provides four different gate intervals TG of 2, 4, 8, or 20 ms respectively. During this interval the D-counter counts up from zero and after closing the gate its content Z is transferred into the D-register where it can be read from the I2C Bus. The IF frequency of SDA 4330-2X is given by fIFFM = Z ; F = , fIFAM = Z

The relations of SDA 4330-2X between gate interval, resolution and measurement range are given in table 1. After being started by setting the IF bit the count-cycle is repeated continuously and the content of the D-register is updated after each cycle. So the first valid result in the D-register can be expected one gate length after starting with an additional delay of100 ms. Afterwards always the latest count is stored in the D-register and SDA 4330-2X can be read via I2C Bus at any time. In order to achieve a valid result after the first gate cycle the control bits for G-counter, F-counter and R-prescaler have to be set to the actual value prior to setting the IF bit.

The I2C Bus interface provides slave receiver and slave transmitter functions. There are two addresses selected by the A0 pin. The I2C-protocol (see diagram 1) contains one string for programming all counters and functions. The transfer of SDA 4330-2X may be stopped optionally after each word if the remaining functions are not to be altered. After power ON all control signals of SDA 4330-2X are undefined, so that the complete write sequence must be executed. In the read mode only the contents of the D-register can be accessed. The programming of the counters and functions is shown in tables 2-4.